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Message-ID: <CAAH4kHY-Gt_6=cGL1VNsgow+XX_3wr_GxRE9hWbHomu+CaAgpw@mail.gmail.com>
Date: Sat, 1 Feb 2025 06:25:34 -0800
From: Dionna Amalie Glaze <dionnaglaze@...gle.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
Paolo Bonzini <pbonzini@...hat.com>, linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
Peter Gonda <pgonda@...gle.com>, Jürgen Groß <jgross@...e.com>,
Kirill Shutemov <kirill.shutemov@...ux.intel.com>, Vitaly Kuznetsov <vkuznets@...hat.com>,
"H . Peter Anvin" <hpa@...or.com>, Binbin Wu <binbin.wu@...el.com>,
Tom Lendacky <thomas.lendacky@....com>, "Yamahata, Isaku" <isaku.yamahata@...el.com>,
"Xiang, Qinglan" <qinglan.xiang@...el.com>, "Xu, Min M" <min.m.xu@...el.com>
Subject: Re: [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX
On Fri, Jan 31, 2025 at 4:50 PM Sean Christopherson <seanjc@...gle.com> wrote:
>
> Attempt to hack around the SNP/TDX guest MTRR disaster by hijacking
> x86_platform.is_untracked_pat_range() to force the legacy PCI hole, i.e.
> memory from TOLUD => 4GiB, as unconditionally writeback.
>
> TDX in particular has created an impossible situation with MTRRs. Because
> TDX disallows toggling CR0.CD, TDX enabling decided the easiest solution
> was to ignore MTRRs entirely (because omitting CR0.CD write is obviously
> too simple).
>
> Unfortunately, under KVM at least, the kernel subtly relies on MTRRs to
> make ACPI play nice with device drivers. ACPI tries to map ranges it finds
> as WB, which in turn prevents device drivers from mapping device memory as
> WC/UC-.
>
> For the record, I hate this hack. But it's the safest approach I can come
> up with. E.g. forcing ioremap() to always use WB scares me because it's
> possible, however unlikely, that the kernel could try to map non-emulated
> memory (that is presented as MMIO to the guest) as WC/UC-, and silently
> forcing those mappings to WB could do weird things.
>
> My initial thought was to effectively revert the offending commit and
> skip the cache disabling/enabling, i.e. the problematic CR0.CD toggling,
> but unfortunately OVMF/EDKII has also added code to skip MTRR setup. :-(
>
EDK2 has a bug tracker. Maybe this is still fixable on Intel's end.
Adding Qinglan, Isaku, and Min to comment.
> Sean Christopherson (2):
> x86/mtrr: Return success vs. "failure" from guest_force_mtrr_state()
> x86/kvm: Override low memory above TOLUD to WB when MTRRs are forced
> WB
>
> arch/x86/include/asm/mtrr.h | 5 +++--
> arch/x86/kernel/cpu/mtrr/generic.c | 11 +++++++----
> arch/x86/kernel/kvm.c | 31 ++++++++++++++++++++++++++++--
> 3 files changed, 39 insertions(+), 8 deletions(-)
>
>
> base-commit: fd8c09ad0d87783b9b6a27900d66293be45b7bad
> --
> 2.48.1.362.g079036d154-goog
>
--
-Dionna Glaze, PhD, CISSP, CCSP (she/her)
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