| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <44468c97-06e6-4bfe-930d-444ab7ead90d@sifive.com>
Date: Sun, 2 Feb 2025 23:43:22 -0600
From: Samuel Holland <samuel.holland@...ive.com>
To: Arnd Bergmann <arnd@...nel.org>, kvm@...r.kernel.org
Cc: Arnd Bergmann <arnd@...db.de>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Huacai Chen <chenhuacai@...nel.org>, Jiaxun Yang <jiaxun.yang@...goat.com>,
Michael Ellerman <mpe@...erman.id.au>, Nicholas Piggin <npiggin@...il.com>,
Christophe Leroy <christophe.leroy@...roup.eu>,
Naveen N Rao <naveen@...nel.org>, Madhavan Srinivasan <maddy@...ux.ibm.com>,
Alexander Graf <graf@...zon.com>, Crystal Wood <crwood@...hat.com>,
Anup Patel <anup@...infault.org>, Atish Patra <atishp@...shpatra.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
<palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Sean Christopherson <seanjc@...gle.com>, Paolo Bonzini
<pbonzini@...hat.com>, Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H. Peter Anvin" <hpa@...or.com>, Vitaly Kuznetsov <vkuznets@...hat.com>,
David Woodhouse <dwmw2@...radead.org>, Paul Durrant <paul@....org>,
Marc Zyngier <maz@...nel.org>, "A. Wilcox" <AWilcox@...cox-Tech.com>,
linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
linuxppc-dev@...ts.ozlabs.org, kvm-riscv@...ts.infradead.org,
linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 2/5] riscv: kvm: drop 32-bit host support
Hi Arnd,
On 2024-12-21 3:42 PM, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@...db.de>
>
> KVM support on RISC-V includes both 32-bit and 64-bit host mode, but in
> practice, all RISC-V SoCs that may use this are 64-bit:
>
> As of linux-6.13, there is no mainline Linux support for any specific
> 32-bit SoC in arch/riscv/, although the generic qemu model should work.
>
> The available RV32 CPU implementations are mostly built for
> microcontroller applications and are lacking a memory management
> unit. There are a few CPU cores with an MMU, but those still lack the
> hypervisor extensions needed for running KVM.
>
> This is unlikely to change in the future, so remove the 32-bit host
> code and simplify the test matrix.
>
> Signed-off-by: Arnd Bergmann <arnd@...db.de>
> ---
> arch/riscv/kvm/Kconfig | 2 +-
> arch/riscv/kvm/aia.c | 105 ------------------------------
> arch/riscv/kvm/aia_imsic.c | 34 ----------
> arch/riscv/kvm/mmu.c | 8 ---
> arch/riscv/kvm/vcpu_exit.c | 4 --
> arch/riscv/kvm/vcpu_insn.c | 12 ----
> arch/riscv/kvm/vcpu_sbi_pmu.c | 8 ---
> arch/riscv/kvm/vcpu_sbi_replace.c | 4 --
> arch/riscv/kvm/vcpu_sbi_v01.c | 4 --
> arch/riscv/kvm/vcpu_timer.c | 20 ------
> 10 files changed, 1 insertion(+), 200 deletions(-)
>
> diff --git a/arch/riscv/kvm/Kconfig b/arch/riscv/kvm/Kconfig
> index 0c3cbb0915ff..7405722e4433 100644
> --- a/arch/riscv/kvm/Kconfig
> +++ b/arch/riscv/kvm/Kconfig
> @@ -19,7 +19,7 @@ if VIRTUALIZATION
>
> config KVM
> tristate "Kernel-based Virtual Machine (KVM) support (EXPERIMENTAL)"
> - depends on RISCV_SBI && MMU
> + depends on RISCV_SBI && MMU && 64BIT
> select HAVE_KVM_IRQCHIP
> select HAVE_KVM_IRQ_ROUTING
> select HAVE_KVM_MSI
> diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c
> index 19afd1f23537..a399a5a9af0e 100644
> --- a/arch/riscv/kvm/aia.c
> +++ b/arch/riscv/kvm/aia.c
> @@ -66,33 +66,6 @@ static inline unsigned long aia_hvictl_value(bool ext_irq_pending)
> return hvictl;
> }
>
> -#ifdef CONFIG_32BIT
> -void kvm_riscv_vcpu_aia_flush_interrupts(struct kvm_vcpu *vcpu)
> -{
> - struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;
> - unsigned long mask, val;
> -
> - if (!kvm_riscv_aia_available())
> - return;
> -
> - if (READ_ONCE(vcpu->arch.irqs_pending_mask[1])) {
> - mask = xchg_acquire(&vcpu->arch.irqs_pending_mask[1], 0);
> - val = READ_ONCE(vcpu->arch.irqs_pending[1]) & mask;
> -
> - csr->hviph &= ~mask;
> - csr->hviph |= val;
> - }
> -}
> -
> -void kvm_riscv_vcpu_aia_sync_interrupts(struct kvm_vcpu *vcpu)
> -{
> - struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;
> -
> - if (kvm_riscv_aia_available())
> - csr->vsieh = ncsr_read(CSR_VSIEH);
> -}
> -#endif
> -
> bool kvm_riscv_vcpu_aia_has_interrupts(struct kvm_vcpu *vcpu, u64 mask)
> {
> int hgei;
> @@ -101,12 +74,6 @@ bool kvm_riscv_vcpu_aia_has_interrupts(struct kvm_vcpu *vcpu, u64 mask)
> if (!kvm_riscv_aia_available())
> return false;
>
> -#ifdef CONFIG_32BIT
> - if (READ_ONCE(vcpu->arch.irqs_pending[1]) &
> - (vcpu->arch.aia_context.guest_csr.vsieh & upper_32_bits(mask)))
> - return true;
> -#endif
> -
> seip = vcpu->arch.guest_csr.vsie;
> seip &= (unsigned long)mask;
> seip &= BIT(IRQ_S_EXT);
> @@ -128,9 +95,6 @@ void kvm_riscv_vcpu_aia_update_hvip(struct kvm_vcpu *vcpu)
> if (!kvm_riscv_aia_available())
> return;
>
> -#ifdef CONFIG_32BIT
> - ncsr_write(CSR_HVIPH, vcpu->arch.aia_context.guest_csr.hviph);
> -#endif
> ncsr_write(CSR_HVICTL, aia_hvictl_value(!!(csr->hvip & BIT(IRQ_VS_EXT))));
> }
>
> @@ -147,22 +111,10 @@ void kvm_riscv_vcpu_aia_load(struct kvm_vcpu *vcpu, int cpu)
> nacl_csr_write(nsh, CSR_VSISELECT, csr->vsiselect);
> nacl_csr_write(nsh, CSR_HVIPRIO1, csr->hviprio1);
> nacl_csr_write(nsh, CSR_HVIPRIO2, csr->hviprio2);
> -#ifdef CONFIG_32BIT
> - nacl_csr_write(nsh, CSR_VSIEH, csr->vsieh);
> - nacl_csr_write(nsh, CSR_HVIPH, csr->hviph);
> - nacl_csr_write(nsh, CSR_HVIPRIO1H, csr->hviprio1h);
> - nacl_csr_write(nsh, CSR_HVIPRIO2H, csr->hviprio2h);
> -#endif
One minor cleanup: since this patch removes all accesses to these 32-bit-only
high-half CSRs, the corresponding members should also be removed from struct
kvm_vcpu_aia_csr in asm/kvm_aia.h.
Regards,
Samuel
Powered by blists - more mailing lists