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Message-ID: <20250203162617.sstmdvv7d3k53izf@thinkpad>
Date: Mon, 3 Feb 2025 21:56:17 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Varadarajan Narayanan <quic_varada@...cinc.com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
vkoul@...nel.org, kishon@...nel.org, andersson@...nel.org,
konradybcio@...nel.org, p.zabel@...gutronix.de,
dmitry.baryshkov@...aro.org, quic_nsekar@...cinc.com,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org,
Praveenkumar I <quic_ipkumar@...cinc.com>,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v7 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes
On Wed, Jan 22, 2025 at 12:04:10PM +0530, Varadarajan Narayanan wrote:
> From: Praveenkumar I <quic_ipkumar@...cinc.com>
>
> Add phy and controller nodes for pcie0_x1 and pcie1_x2.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@...cinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
One minor comment below.
[...]
> + assigned-clocks = <&gcc GCC_PCIE3X2_AUX_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_M_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
> + <&gcc GCC_PCIE3X2_AXI_S_CLK>,
> + <&gcc GCC_PCIE3X2_RCHG_CLK>;
> +
> + assigned-clock-rates = <2000000>,
> + <266666666>,
> + <240000000>,
> + <240000000>,
> + <100000000>;
> +
Does the drivers really need to set clock rate for these many clocks?
No, as per the reply to my similar question to IPQ5424:
https://lore.kernel.org/linux-arm-msm/9206e44c-da4f-4bdb-850f-fac511f4ddc7@quicinc.com/
- Mani
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