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Message-Id: <20250203-drm-msm-phy-pll-cfg-reg-v2-0-862b136c5d22@linaro.org>
Date: Mon, 03 Feb 2025 18:29:17 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v2 0/4] drm/msm/dsi/phy: Improvements around concurrent
PHY_CMN_CLK_CFG[01]
Changes in v2:
- Add Fixes tag
- New patch #4
- Link to v1: https://lore.kernel.org/r/20250131-drm-msm-phy-pll-cfg-reg-v1-0-3b99efeb2e8d@linaro.org
Calling these improvements, not fixes, because I don't think we ever hit
actual concurrency issue. Although if we ever hit it, it would be very
tricky to debug and find the cause.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (4):
drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG0 updated from driver side
drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver
drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1 when choosing bitclk source
drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 70 ++++++++++++++--------
.../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 12 +++-
2 files changed, 55 insertions(+), 27 deletions(-)
---
base-commit: 3270483b5a99a2ada44c72d6c2ae20d77c6e5c28
change-id: 20250131-drm-msm-phy-pll-cfg-reg-7e5bf5aa9df6
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
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