linux-kernel - Re: [PATCH] perf/x86/intel: Ensure LBRs are disabled when a CPU is starting

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Message-ID: <20250203114310.GF505@noisy.programming.kicks-ass.net>
Date: Mon, 3 Feb 2025 12:43:10 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Sean Christopherson <seanjc@...gle.com>
Cc: Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
	linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
	Maxim Levitsky <mlevitsk@...hat.com>
Subject: Re: [PATCH] perf/x86/intel: Ensure LBRs are disabled when a CPU is
 starting

On Thu, Jan 30, 2025 at 05:07:21PM -0800, Sean Christopherson wrote:
> Explicitly clear DEBUGCTL.LBR when a CPU is starting, prior to purging the
> LBR MSRs themselves, as at least one system has been found to transfer
> control to the kernel with LBRs enabled (it's unclear whether it's a BIOS
> flaw or a CPU goof).  Because the kernel preserves the original DEBUGCTL,
> even when toggling LBRs, leaving DEBUGCTL.LBR as is results in running
> with LBRs enabled at all times.
> 
> Reported-by: Maxim Levitsky <mlevitsk@...hat.com>
> Closes: https://lore.kernel.org/all/c9d8269bff69f6359731d758e3b1135dedd7cc61.camel@redhat.com
> Reviewed-by: Maxim Levitsky <mlevitsk@...hat.com>
> Cc: stable@...r.kernel.org
> Signed-off-by: Sean Christopherson <seanjc@...gle.com>
> ---
>  arch/x86/events/intel/core.c     | 5 ++++-
>  arch/x86/include/asm/msr-index.h | 3 ++-
>  2 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index e76e892f44cd..efd069bc9c28 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -5038,8 +5038,11 @@ static void intel_pmu_cpu_starting(int cpu)
>  
>  	init_debug_store_on_cpu(cpu);
>  	/*
> -	 * Deal with CPUs that don't clear their LBRs on power-up.
> +	 * Deal with CPUs that don't clear their LBRs on power-up, and that may
> +	 * even boot with LBRs enabled.
>  	 */
> +	if (!static_cpu_has(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
> +		msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
>  	intel_pmu_lbr_reset();

Gotta love this stuff.

Thanks!