linux-kernel - Re: [PATCH 0/3] Add support to reconfigure PLL

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <15d16afd-8e1a-479f-9573-8845d1408178@quicinc.com>
Date: Tue, 4 Feb 2025 23:13:08 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Johan Hovold <johan@...nel.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Michael Turquette
	<mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Ajit Pandey
	<quic_ajipan@...cinc.com>,
        Imran Shaik <quic_imrashai@...cinc.com>,
        "Jagadeesh Kona" <quic_jkona@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/3] Add support to reconfigure PLL



On 2/4/2025 3:38 PM, Johan Hovold wrote:
> On Mon, Jan 13, 2025 at 10:57:03PM +0530, Taniya Das wrote:
>> During boot-up, there is a possibility that the PLL configuration might
>> be missed even after invoking pll_configure() from the clock controller
>> probe. This is often due to the PLL being connected to rail or rails
>> that are in an OFF state and current clock controller also cannot vote
>> on multiple rails. As a result, the PLL may be enabled with suboptimal
>> settings, leading to functional issues.
>>
>> The PLL configuration, now part of clk_alpha_pll, can be reused to
>> reconfigure the PLL to a known good state before scaling for frequency.
>> The 'clk_alpha_pll_reconfigure()' can be updated to support more PLLs
>> in future.
> 
> This sounds like a hack. You already describe the underlying problem (and
> indirectly its solution) in the first paragraph above, namely that the
> video clock controller has not enabled the power domain needed to
> configure the PLL.
> 

This is not a hack, but another alternative way to ensure the PLL is 
configured to the right configuration before being used.

> I believe support for clock controllers that need to enable multiple
> power domains is on its way into 6.15:
> 
> 	https://lore.kernel.org/lkml/20250117-b4-linux-next-24-11-18-clock-multiple-power-domains-v10-0-13f2bb656dad@linaro.org/
> 
> Perhaps that's what you need to fix this properly.
> 

Yes, this is just to add a dependency on clock controller to put the 
rail vote, but this series does not fully solve the clock controller's 
PLL requirement problems.

>> The IRIS driver support added
>> https://lore.kernel.org/all/20241212-qcom-video-iris-v9-0-e8c2c6bd4041@quicinc.com/
>> observes the pll latch warning during boot up due to the dependency of
>> the PLL not in good state, thus add config support for SM8550 Video
>> clock controller PLLs.
> 
>> Taniya Das (3):
>>        clk: qcom: clk-alpha-pll: Integrate PLL configuration into PLL structure
>>        clk: qcom: clk-alpha-pll: Add support to reconfigure PLL
>>        clk: qcom: videocc-sm8550: Update the pll config for Video PLLs
> 
> Johan

-- 
Thanks & Regards,
Taniya Das.