linux-kernel - [PATCH v1 1/3] dt-bindings: i3c: Add Qualcomm I3C master controller bindings

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250205143109.2955321-2-quic_msavaliy@quicinc.com>
Date: Wed,  5 Feb 2025 20:01:07 +0530
From: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
To: alexandre.belloni@...tlin.com, robh@...nel.org, krzk+dt@...nel.org,
        conor+dt@...nel.org, jarkko.nikula@...ux.intel.com,
        linux-i3c@...ts.infradead.org, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
Subject: [PATCH v1 1/3] dt-bindings: i3c: Add Qualcomm I3C master controller bindings

Add device tree bindings for the Qualcomm I3C master controller. This
includes the necessary documentation and properties required to describe
the hardware in the device tree.

Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
---
 .../bindings/i3c/qcom,i3c-master.yaml         | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml

diff --git a/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml
new file mode 100644
index 000000000000..ad63ea779fd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/qcom,i3c-master.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm I3C master controller
+
+maintainers:
+  - Mukesh Kumar Savaliya <quic_msavaliy@...cinc.com>
+
+allOf:
+  - $ref: i3c.yaml#
+
+properties:
+  compatible:
+    const: qcom,geni-i3c
+
+  reg:
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    minItems: 1
+
+  clock-names:
+    items:
+      - const: se-clk
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 3
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts-extended
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+
+    i3c@...000 {
+        compatible = "qcom,geni-i3c";
+        reg = <0x00884000 0x4000>;
+        clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+        clock-names = "se-clk";
+        interrupts-extended = <&intc GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <3>;
+        #size-cells = <0>;
+    };
+...
-- 
2.25.1