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Message-ID: <f4jlvjkwrw37v4dkelvispo2nnl7hkkxczjb3rk47sjpss6bnc@nsdk7qo3c7lg>
Date: Wed, 5 Feb 2025 04:48:23 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Jessica Zhang <quic_jesszhan@...cinc.com>
Cc: Rob Clark <robdclark@...il.com>, quic_abhinavk@...cinc.com,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Simona Vetter <simona@...ll.ch>, Simona Vetter <simona.vetter@...ll.ch>,
quic_ebharadw@...cinc.com, linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org, Rob Clark <robdclark@...omium.org>,
Ville Syrjälä <ville.syrjala@...ux.intel.com>
Subject: Re: [PATCH v5 07/14] drm/msm/dpu: Reserve resources for CWB
On Tue, Feb 04, 2025 at 01:29:23PM -0800, Jessica Zhang wrote:
>
>
> On 1/29/2025 2:11 PM, Dmitry Baryshkov wrote:
> > On Tue, Jan 28, 2025 at 07:20:39PM -0800, Jessica Zhang wrote:
> > > Add support for RM to reserve dedicated CWB PINGPONGs and CWB muxes
> > >
> > > For concurrent writeback, even-indexed CWB muxes must be assigned to
> > > even-indexed LMs and odd-indexed CWB muxes for odd-indexed LMs. The same
> > > even/odd rule applies for dedicated CWB PINGPONGs.
> > >
> > > Track the CWB muxes in the global state and add a CWB-specific helper to
> > > reserve the correct CWB muxes and dedicated PINGPONGs following the
> > > even/odd rule.
> > >
> > > Signed-off-by: Jessica Zhang <quic_jesszhan@...cinc.com>
> > >
> > > ---
> > > Changes in v5:
> > > - Allocate CWB muxes first then allocate PINGPONG block based on CWB mux
> > > index
> > > - Corrected comment doc on odd/even rule
> > > ---
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 34 ++++++++++--
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
> > > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 82 +++++++++++++++++++++++++++++
> > > 4 files changed, 115 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > index 99db194f5d095e83ac72f2830814e649a25918ef..17bd9762f56a392e8e9e8d7c897dcb6e06bccbb3 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > > @@ -2,7 +2,7 @@
> > > /*
> > > * Copyright (C) 2013 Red Hat
> > > * Copyright (c) 2014-2018, 2020-2021 The Linux Foundation. All rights reserved.
> > > - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> > > + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
> > > *
> > > * Author: Rob Clark <robdclark@...il.com>
> > > */
> > > @@ -28,6 +28,7 @@
> > > #include "dpu_hw_dsc.h"
> > > #include "dpu_hw_merge3d.h"
> > > #include "dpu_hw_cdm.h"
> > > +#include "dpu_hw_cwb.h"
> > > #include "dpu_formats.h"
> > > #include "dpu_encoder_phys.h"
> > > #include "dpu_crtc.h"
> > > @@ -133,6 +134,9 @@ enum dpu_enc_rc_states {
> > > * @cur_slave: As above but for the slave encoder.
> > > * @hw_pp: Handle to the pingpong blocks used for the display. No.
> > > * pingpong blocks can be different than num_phys_encs.
> > > + * @hw_cwb: Handle to the CWB muxes used for concurrent writeback
> > > + * display. Number of CWB muxes can be different than
> > > + * num_phys_encs.
> > > * @hw_dsc: Handle to the DSC blocks used for the display.
> > > * @dsc_mask: Bitmask of used DSC blocks.
> > > * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> > > @@ -177,6 +181,7 @@ struct dpu_encoder_virt {
> > > struct dpu_encoder_phys *cur_master;
> > > struct dpu_encoder_phys *cur_slave;
> > > struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> > > + struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
> > > struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> > > unsigned int dsc_mask;
> > > @@ -1137,7 +1142,10 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> > > struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
> > > struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> > > struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> > > + struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];
> > > int num_ctl, num_pp, num_dsc;
> > > + int num_cwb = 0;
> > > + bool is_cwb_encoder;
> > > unsigned int dsc_mask = 0;
> > > int i;
> > > @@ -1151,6 +1159,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> > > priv = drm_enc->dev->dev_private;
> > > dpu_kms = to_dpu_kms(priv->kms);
> > > + is_cwb_encoder = drm_crtc_in_clone_mode(crtc_state) &&
> > > + dpu_enc->disp_info.intf_type == INTF_WB;
> > > global_state = dpu_kms_get_existing_global_state(dpu_kms);
> > > if (IS_ERR_OR_NULL(global_state)) {
> > > @@ -1161,9 +1171,25 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> > > trace_dpu_enc_mode_set(DRMID(drm_enc));
> > > /* Query resource that have been reserved in atomic check step. */
> > > - num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > > - drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp,
> > > - ARRAY_SIZE(hw_pp));
> > > + if (is_cwb_encoder) {
> > > + num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > > + drm_enc->crtc,
> > > + DPU_HW_BLK_DCWB_PINGPONG,
> > > + hw_pp, ARRAY_SIZE(hw_pp));
> > > + num_cwb = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > > + drm_enc->crtc,
> > > + DPU_HW_BLK_CWB,
> > > + hw_cwb, ARRAY_SIZE(hw_cwb));
> > > + } else {
> > > + num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > > + drm_enc->crtc,
> > > + DPU_HW_BLK_PINGPONG, hw_pp,
> > > + ARRAY_SIZE(hw_pp));
> > > + }
> > > +
> > > + for (i = 0; i < num_cwb; i++)
> > > + dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]);
> > > +
> > > num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > > drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > > index ba7bb05efe9b8cac01a908e53121117e130f91ec..8d820cd1b5545d247515763039b341184e814e32 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> > > @@ -77,12 +77,14 @@ enum dpu_hw_blk_type {
> > > DPU_HW_BLK_LM,
> > > DPU_HW_BLK_CTL,
> > > DPU_HW_BLK_PINGPONG,
> > > + DPU_HW_BLK_DCWB_PINGPONG,
> > > DPU_HW_BLK_INTF,
> > > DPU_HW_BLK_WB,
> > > DPU_HW_BLK_DSPP,
> > > DPU_HW_BLK_MERGE_3D,
> > > DPU_HW_BLK_DSC,
> > > DPU_HW_BLK_CDM,
> > > + DPU_HW_BLK_CWB,
> > > DPU_HW_BLK_MAX,
> > > };
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > index 54ef6cfa2485a8a3886bd26b7ec3692d037dc35e..a57ec2ec106083e8f93578e4307e8b13ae549c08 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> > > @@ -132,6 +132,7 @@ struct dpu_global_state {
> > > uint32_t cdm_to_crtc_id;
> > > uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE];
> > > + uint32_t cwb_to_crtc_id[CWB_MAX - CWB_0];
> > > };
> > > struct dpu_global_state
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > index dca3107d1e8265a864ac62d6b845d6cb966965ed..2d5cf97a75913d51b2568ce85ec0c79a4a34deb4 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> > > @@ -233,6 +233,54 @@ static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx)
> > > return -EINVAL;
> > > }
> > > +static int _dpu_rm_reserve_cwb_mux_and_pingpongs(struct dpu_rm *rm,
> > > + struct dpu_global_state *global_state,
> > > + uint32_t crtc_id,
> > > + struct msm_display_topology *topology)
> > > +{
> > > + int num_cwb_mux = topology->num_lm, cwb_mux_count = 0;
> > > + int cwb_pp_start_idx = PINGPONG_CWB_0 - PINGPONG_0;
> > > + int cwb_pp_idx[MAX_BLOCKS];
> > > + int cwb_mux_idx[MAX_BLOCKS];
> > > +
> > > + /*
> > > + * Reserve additional dedicated CWB PINGPONG blocks and muxes for each
> > > + * mixer
> > > + *
> > > + * TODO: add support reserving resources for platforms with no
> > > + * PINGPONG_CWB
> > > + */
> > > + for (int i = 0; i < ARRAY_SIZE(rm->mixer_blks) &&
> > > + cwb_mux_count < num_cwb_mux; i++) {
> > > + for (int j = 0; j < ARRAY_SIZE(rm->cwb_blks); j++) {
> > > + /*
> > > + * Odd LMs must be assigned to odd CWB muxes and even
> > > + * LMs with even CWB muxes
> > > + */
> > > + if (reserved_by_other(global_state->cwb_to_crtc_id, j, crtc_id) ||
> > > + i % 2 != j % 2)
> >
> > Should't it be a loop over allocated LMs with the check that
> > lm[i]->idx % 2 != j % 2 ?
> > Otherwise you are looping over some random LMs and trying to match CWB
> > indices against them.
>
> Hi Dmitry,
>
> The RM array idx are based of the hw block ids [1] so there isn't much
> difference using i and lm[i]->id.
Ack. Please add a comment (as I think there will be another revision).
>
> Thanks,
>
> Jessica Zhang
>
> [1] https://elixir.bootlin.com/linux/v6.13.1/source/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c#L74
>
--
With best wishes
Dmitry
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