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Message-Id: <20250205222223.613-2-wachiturroxd150@gmail.com>
Date: Wed, 5 Feb 2025 22:22:15 +0000
From: Denzeel Oliva <wachiturroxd150@...il.com>
To: krzk@...nel.org,
alim.akhtar@...sung.com
Cc: linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org,
Denzeel Oliva <wachiturroxd150@...il.com>
Subject: [PATCH v1 1/9] dt-bindings: clock: samsung,exynos990-clock: add PERIC0/1 clock management unit
Add dt-schema documentation for
the Connectivity Peripheral 0 / 1 (PERIC0/1) clock management unit.
Signed-off-by: Denzeel Oliva <wachiturroxd150@...il.com>
---
.../clock/samsung,exynos990-clock.yaml | 24 +++
include/dt-bindings/clock/samsung,exynos990.h | 178 +++++++++++++++++-
2 files changed, 201 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
index 9e7944b5f..6b053d1bc 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml
@@ -30,6 +30,8 @@ description: |
properties:
compatible:
enum:
+ - samsung,exynos990-cmu-peric1
+ - samsung,exynos990-cmu-peric0
- samsung,exynos990-cmu-hsi0
- samsung,exynos990-cmu-top
@@ -55,6 +57,28 @@ required:
- reg
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - samsung,exynos990-cmu-peric1
+ - samsung,exynos990-cmu-peric0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
+ - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: ip
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h
index 307215a3f..97cb5e8d2 100644
--- a/include/dt-bindings/clock/samsung,exynos990.h
+++ b/include/dt-bindings/clock/samsung,exynos990.h
@@ -233,4 +233,180 @@
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
-#endif
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER 1
+#define CLK_MOUT_PERIC0_USI00_USI_USER 2
+#define CLK_MOUT_PERIC0_USI01_USI_USER 3
+#define CLK_MOUT_PERIC0_USI02_USI_USER 4
+#define CLK_MOUT_PERIC0_USI03_USI_USER 5
+#define CLK_MOUT_PERIC0_USI04_USI_USER 6
+#define CLK_MOUT_PERIC0_USI05_USI_USER 7
+#define CLK_MOUT_PERIC0_USI_I2C_USER 8
+#define CLK_MOUT_PERIC0_UART_DBG 9
+#define CLK_MOUT_PERIC0_USI13_USI_USER 10
+#define CLK_MOUT_PERIC0_USI14_USI_USER 11
+#define CLK_MOUT_PERIC0_USI15_USI_USER 12
+#define CLK_DOUT_PERIC0_USI00_USI 13
+#define CLK_DOUT_PERIC0_USI01_USI 14
+#define CLK_DOUT_PERIC0_USI02_USI 15
+#define CLK_DOUT_PERIC0_USI03_USI 16
+#define CLK_DOUT_PERIC0_USI04_USI 17
+#define CLK_DOUT_PERIC0_USI05_USI 18
+#define CLK_DOUT_PERIC0_USI_I2C 19
+#define CLK_DOUT_PERIC0_UART_DBG 20
+#define CLK_DOUT_PERIC0_USI13_USI 21
+#define CLK_DOUT_PERIC0_USI14_USI 22
+#define CLK_DOUT_PERIC0_USI15_USI 23
+#define CLK_GOUT_PERIC0_GPIO_PCLK 24
+#define CLK_GOUT_PERIC0_SYSREG_PCLK 25
+#define CLK_GOUT_PERIC0_CMU_PCLK 26
+#define CLK_GOUT_PERIC0_BUSP_CLK 27
+#define CLK_GOUT_PERIC0_OSCCLK_CLK 28
+#define CLK_GOUT_PERIC0_USI00_USI_CLK 29
+#define CLK_GOUT_PERIC0_USI_I2C_CLK 30
+#define CLK_GOUT_PERIC0_USI01_USI_CLK 31
+#define CLK_GOUT_PERIC0_USI02_USI_CLK 32
+#define CLK_GOUT_PERIC0_USI03_USI_CLK 33
+#define CLK_GOUT_PERIC0_USI04_USI_CLK 34
+#define CLK_GOUT_PERIC0_USI05_USI_CLK 35
+#define CLK_GOUT_PERIC0_UART_DBG_CLK 36
+#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 37
+#define CLK_GOUT_PERIC0_USI13_USI_CLK 38
+#define CLK_GOUT_PERIC0_USI14_USI_CLK 39
+#define CLK_GOUT_PERIC0_D_TZPC_PCLK 40
+#define CLK_GOUT_PERIC0_USI15_USI_CLK 41
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 42
+#define CLK_GOUT_PERIC0_TOP0_PCLK_4 43
+#define CLK_GOUT_PERIC0_TOP0_PCLK_5 44
+#define CLK_GOUT_PERIC0_TOP0_PCLK_6 45
+#define CLK_GOUT_PERIC0_TOP0_PCLK_7 46
+#define CLK_GOUT_PERIC0_TOP0_PCLK_8 47
+#define CLK_GOUT_PERIC0_TOP0_PCLK_9 48
+#define CLK_GOUT_PERIC0_TOP0_PCLK_10 49
+#define CLK_GOUT_PERIC0_TOP0_PCLK_11 50
+#define CLK_GOUT_PERIC0_TOP0_PCLK_12 51
+#define CLK_GOUT_PERIC0_TOP0_PCLK_13 52
+#define CLK_GOUT_PERIC0_TOP0_PCLK_14 53
+#define CLK_GOUT_PERIC0_TOP0_PCLK_15 54
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 55
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 56
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 57
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 58
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 59
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 60
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 61
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 62
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 63
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 64
+#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 65
+#define CLK_GOUT_PERIC0_TOP1_PCLK_0 66
+#define CLK_GOUT_PERIC0_TOP1_PCLK_3 67
+#define CLK_GOUT_PERIC0_TOP1_PCLK_4 68
+#define CLK_GOUT_PERIC0_TOP1_PCLK_5 69
+#define CLK_GOUT_PERIC0_TOP1_PCLK_6 70
+#define CLK_GOUT_PERIC0_TOP1_PCLK_7 71
+#define CLK_GOUT_PERIC0_TOP1_PCLK_8 72
+#define CLK_GOUT_PERIC0_TOP1_PCLK_15 73
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 74
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 75
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 76
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 77
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 78
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 79
+#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 80
+
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER 1
+#define CLK_MOUT_PERIC1_UART_BT_USER 2
+#define CLK_MOUT_PERIC1_USI_I2C_USER 3
+#define CLK_MOUT_PERIC1_USI06_USI_USER 4
+#define CLK_MOUT_PERIC1_USI07_USI_USER 5
+#define CLK_MOUT_PERIC1_USI08_USI_USER 6
+#define CLK_MOUT_PERIC1_USI09_USI_USER 7
+#define CLK_MOUT_PERIC1_USI10_USI_USER 8
+#define CLK_MOUT_PERIC1_USI11_USI_USER 9
+#define CLK_MOUT_PERIC1_USI12_USI_USER 10
+#define CLK_MOUT_PERIC1_USI18_USI_USER 11
+#define CLK_MOUT_PERIC1_USI16_USI_USER 12
+#define CLK_MOUT_PERIC1_USI17_USI_USER 13
+#define CLK_DOUT_PERIC1_UART_BT 14
+#define CLK_DOUT_PERIC1_USI_I2C 15
+#define CLK_DOUT_PERIC1_USI06_USI 16
+#define CLK_DOUT_PERIC1_USI07_USI 17
+#define CLK_DOUT_PERIC1_USI08_USI 18
+#define CLK_DOUT_PERIC1_USI18_USI 19
+#define CLK_DOUT_PERIC1_USI12_USI 20
+#define CLK_DOUT_PERIC1_USI09_USI 21
+#define CLK_DOUT_PERIC1_USI10_USI 22
+#define CLK_DOUT_PERIC1_USI11_USI 23
+#define CLK_DOUT_PERIC1_USI16_USI 24
+#define CLK_DOUT_PERIC1_USI17_USI 25
+#define CLK_GOUT_PERIC1_GPIO_PCLK 26
+#define CLK_GOUT_PERIC1_SYSREG_PCLK 27
+#define CLK_GOUT_PERIC1_CMU_PCLK 28
+#define CLK_GOUT_PERIC1_BUSP_CLK 29
+#define CLK_GOUT_PERIC1_USI06_USI_CLK 30
+#define CLK_GOUT_PERIC1_USI07_USI_CLK 31
+#define CLK_GOUT_PERIC1_USI08_USI_CLK 32
+#define CLK_GOUT_PERIC1_USI09_USI_CLK 33
+#define CLK_GOUT_PERIC1_USI10_USI_CLK 34
+#define CLK_GOUT_PERIC1_USI_I2C_CLK 35
+#define CLK_GOUT_PERIC1_UART_BT_CLK 36
+#define CLK_GOUT_PERIC1_USI12_USI_CLK 37
+#define CLK_GOUT_PERIC1_USI18_USI_CLK 38
+#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 39
+#define CLK_GOUT_PERIC1_USI11_USI_CLK 40
+#define CLK_GOUT_PERIC1_D_TZPC_PCLK 41
+#define CLK_GOUT_PERIC1_USI16_USI_CLK 42
+#define CLK_GOUT_PERIC1_USI17_USI_CLK 43
+#define CLK_GOUT_PERIC1_TOP0_PCLK_4 44
+#define CLK_GOUT_PERIC1_TOP0_PCLK_10 45
+#define CLK_GOUT_PERIC1_TOP0_PCLK_11 46
+#define CLK_GOUT_PERIC1_TOP0_PCLK_12 47
+#define CLK_GOUT_PERIC1_TOP0_PCLK_13 48
+#define CLK_GOUT_PERIC1_TOP0_PCLK_14 49
+#define CLK_GOUT_PERIC1_TOP0_PCLK_15 50
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 51
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 52
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 53
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 54
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 55
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 56
+#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 57
+#define CLK_GOUT_PERIC1_TOP1_PCLK_1 58
+#define CLK_GOUT_PERIC1_TOP1_PCLK_0 59
+#define CLK_GOUT_PERIC1_TOP1_PCLK_2 60
+#define CLK_GOUT_PERIC1_TOP1_PCLK_3 61
+#define CLK_GOUT_PERIC1_TOP1_PCLK_4 62
+#define CLK_GOUT_PERIC1_TOP1_PCLK_5 63
+#define CLK_GOUT_PERIC1_TOP1_PCLK_6 64
+#define CLK_GOUT_PERIC1_TOP1_PCLK_7 65
+#define CLK_GOUT_PERIC1_TOP1_PCLK_9 66
+#define CLK_GOUT_PERIC1_TOP1_PCLK_10 67
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 68
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 69
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 70
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 71
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 72
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 73
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 74
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 75
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 76
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 77
+#define CLK_GOUT_PERIC1_OSCCLK_CLK 78
+#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 79
+#define CLK_GOUT_PERIC1_XIU_P_ACLK 80
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 81
+#define CLK_GOUT_PERIC1_TOP1_PCLK_12 82
+#define CLK_GOUT_PERIC1_TOP1_PCLK_13 83
+#define CLK_GOUT_PERIC1_TOP1_PCLK_14 84
+#define CLK_GOUT_PERIC1_TOP1_PCLK_15 85
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 86
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 87
+#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 88
+#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 89
+#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 90
+#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91
+#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 92
+
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS990_H */
--
2.47.1
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