linux-kernel - Re: [PATCH v1 1/1] MAINTAINERS: Add pin control and GPIO to the Intel MID record

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Message-ID: <Z6MaNI2SiWLKyE2k@smile.fi.intel.com>
Date: Wed, 5 Feb 2025 09:58:44 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc: linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 1/1] MAINTAINERS: Add pin control and GPIO to the
 Intel MID record

On Wed, Feb 05, 2025 at 07:40:06AM +0200, Mika Westerberg wrote:
> On Tue, Feb 04, 2025 at 07:37:17PM +0200, Andy Shevchenko wrote:
> > On Tue, Feb 04, 2025 at 07:01:00PM +0200, Andy Shevchenko wrote:
> > > Intel MID record is not listed all related files. Add to there
> > > pin control and GPIO drivers along with HSU (High Speed UART)
> > > and HSU DMA.
> > 
> > Mika, JFYI, it's supposed to go via Intel pin control tree.
> 
> Got it :)
> 
> Acked-by: Mika Westerberg <mika.westerberg@...ux.intel.com>

Pushed to my review and testing queue, thanks!

-- 
With Best Regards,
Andy Shevchenko