[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250205084531.158763-3-yung-chuan.liao@linux.intel.com>
Date: Wed, 5 Feb 2025 16:45:16 +0800
From: Bard Liao <yung-chuan.liao@...ux.intel.com>
To: linux-sound@...r.kernel.org,
vkoul@...nel.org
Cc: vinod.koul@...aro.org,
linux-kernel@...r.kernel.org,
pierre-louis.bossart@...ux.dev,
bard.liao@...el.com
Subject: [PATCH 02/16] soundwire: cadence: add BTP support for DP0
From: Pierre-Louis Bossart <pierre-louis.bossart@...ux.dev>
The register definitions are missing a BULK_ENABLE bitfield which must
be set for DP0.
In addition, the existing mapping from PDI to Data Port is 1:1. That's
fine for PCM streams which are by construction in one direction
only. The BTP/BRA protocol is bidirectional and relies on DP0 only,
which breaks the 1:1 mapping. DP0 MUST be mapped to both PDI0 and
PDI1, with PDI0 taking care of the TX direction and PDI1 of the RX
direction.
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.dev>
Signed-off-by: Bard Liao <yung-chuan.liao@...ux.intel.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@...ux.intel.com>
Reviewed-by: Liam Girdwood <liam.r.girdwood@...el.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>
---
drivers/soundwire/cadence_master.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/cadence_master.c b/drivers/soundwire/cadence_master.c
index f367670ea991..f7654a7fd53f 100644
--- a/drivers/soundwire/cadence_master.c
+++ b/drivers/soundwire/cadence_master.c
@@ -184,6 +184,7 @@ MODULE_PARM_DESC(cdns_mcp_int_mask, "Cadence MCP IntMask");
#define CDNS_PORTCTRL_TEST_FAILED BIT(1)
#define CDNS_PORTCTRL_DIRN BIT(7)
#define CDNS_PORTCTRL_BANK_INVERT BIT(8)
+#define CDNS_PORTCTRL_BULK_ENABLE BIT(16)
#define CDNS_PORT_OFFSET 0x80
@@ -1901,13 +1902,20 @@ void sdw_cdns_config_stream(struct sdw_cdns *cdns,
if (cdns->bus.params.m_data_mode != SDW_PORT_DATA_MODE_NORMAL)
val |= CDNS_PORTCTRL_TEST_FAILED;
+ } else if (pdi->num == 0 || pdi->num == 1) {
+ val |= CDNS_PORTCTRL_BULK_ENABLE;
}
offset = CDNS_PORTCTRL + pdi->num * CDNS_PORT_OFFSET;
cdns_updatel(cdns, offset,
- CDNS_PORTCTRL_DIRN | CDNS_PORTCTRL_TEST_FAILED,
+ CDNS_PORTCTRL_DIRN | CDNS_PORTCTRL_TEST_FAILED |
+ CDNS_PORTCTRL_BULK_ENABLE,
val);
- val = pdi->num;
+ /* The DataPort0 needs to be mapped to both PDI0 and PDI1 ! */
+ if (pdi->num == 1)
+ val = 0;
+ else
+ val = pdi->num;
val |= CDNS_PDI_CONFIG_SOFT_RESET;
val |= FIELD_PREP(CDNS_PDI_CONFIG_CHANNEL, (1 << ch) - 1);
cdns_writel(cdns, CDNS_PDI_CONFIG(pdi->num), val);
--
2.43.0
Powered by blists - more mailing lists