linux-kernel - Re: [PATCH v2 2/3] Revert "arm64: dts: rockchip: Increase VOP clk rate on RK3328"

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Message-ID: <b85a4449-f178-4877-9ba7-65ddcc231052@rock-chips.com>
Date: Wed, 5 Feb 2025 10:18:38 +0800
From: zhangqing <zhangqing@...k-chips.com>
To: Jonas Karlman <jonas@...boo.se>
Cc: mturquette@...libre.com, sboyd@...nel.org, kever.yang@...k-chips.com,
 heiko@...ech.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, huangtao@...k-chips.com,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 2/3] Revert "arm64: dts: rockchip: Increase VOP clk
 rate on RK3328"


在 2025/1/26 5:39, Jonas Karlman 写道:
> Hi Elaine,
>
> On 2025-01-25 02:15, Elaine Zhang wrote:
>> This reverts commit 0f2ddb128fa20f8441d903285632f2c69e90fae1.
>>
>> Before changing the PLL frequency, in order to avoid overclocking the
>> child clock, set the child clock to a large div first, and then set the
>> CLK as required after the PLL is set.
> This commit message does not match what this patch does. In this patch
> you revert a change and in next patch you re-introduce same thing
> slightly different.
>
> As mentioned in v1, see [1], you should merge both patches as a single
> fix, if a fix really is needed.
Ok, This will be fixed in the next release.
>
> Testing on a rk3328-rock64 I see no difference before or after these
> changes. Please describe what this fixes because clk_summary show same
> clock tree and rates before and after this fix.
The clock tree might see the same result.

It is not safe or correct to set the child clock frequency before 
setting the PLL frequency, and the parent clock PLL frequency may not be 
the final expected value at this time.
Therefore, the correct setting of the child clock frequency should be 
after the PLL frequency is set.

The partial clock is set before the PLL setting frequency, which is to 
prevent the child clock from overclocking when the PLL is set, so ensure 
that the child clock is at a safe frequency before setting the PLL, and 
reset the child clock frequency after the PLL is set.
>
> Also for next revert patch you send, please include the patch author in
> the recipient list :-)
>
> [1] https://lore.kernel.org/all/cae9cb0a-1500-4fbc-bbf4-a6266549bcb9@kwiboo.se/
>
> Regards,
> Jonas
>
>> Fixes: 0f2ddb128fa2 ("arm64: dts: rockchip: Increase VOP clk rate on RK3328")
>>
>> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3328.dtsi | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
>> index 7d992c3c01ce..f3ef8cbfbdae 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
>> @@ -852,8 +852,8 @@
>>   			<0>, <24000000>,
>>   			<24000000>, <24000000>,
>>   			<15000000>, <15000000>,
>> -			<300000000>, <100000000>,
>> -			<400000000>, <100000000>,
>> +			<100000000>, <100000000>,
>> +			<100000000>, <100000000>,
>>   			<50000000>, <100000000>,
>>   			<100000000>, <100000000>,
>>   			<50000000>, <50000000>,
>
-- 
张晴
瑞芯微电子股份有限公司
Rockchip Electronics Co.,Ltd
地址：福建省福州市铜盘路软件大道89号软件园A区21号楼
Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China
Tel:+86-0591-83991906-8601
邮编：350003
E-mail:elaine.zhang@...k-chips.com
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