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Message-ID: <CAJM55Z9s4FMCmGaGPGBdcJWxoTNO1gupMLAq2a1fExiho5W1jw@mail.gmail.com>
Date: Wed, 5 Feb 2025 02:18:57 -0800
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: E Shattow <e@...eshell.de>, Emil Renner Berthing <kernel@...il.dk>, Conor Dooley <conor@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, Hal Feng <hal.feng@...rfivetech.com>
Subject: Re: [PATCH v2 2/5] riscv: dts: starfive: jh7110-common: qspi flash
setting read-delay 2 cycles max 100MHz
E Shattow wrote:
> Sync qspi flash setting to read-delay=2 and spi-max-frequency 100MHz for
> better compatibility with operating system and downstream boot loader SPL
> secondary program loader.
Here you should be explaining why these values better describe the hardware. To
me this just reads as "u-boot does this, so let's do the same" whith doesn't
really explain anything.
/Emil
>
> Signed-off-by: E Shattow <e@...eshell.de>
> Reviewed-by: Hal Feng <hal.feng@...rfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index a5661b677687..8a59c3001339 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -317,8 +317,8 @@ &qspi {
> nor_flash: flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> - cdns,read-delay = <5>;
> - spi-max-frequency = <12000000>;
> + cdns,read-delay = <2>;
> + spi-max-frequency = <100000000>;
> cdns,tshsl-ns = <1>;
> cdns,tsd2d-ns = <1>;
> cdns,tchsh-ns = <1>;
> --
> 2.47.2
>
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