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Message-ID: <Z6NCSo98YRgG666Q@hu-varada-blr.qualcomm.com>
Date: Wed, 5 Feb 2025 16:19:46 +0530
From: Varadarajan Narayanan <quic_varada@...cinc.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
CC: <bhelgaas@...gle.com>, <lpieralisi@...nel.org>, <kw@...ux.com>,
        <manivannan.sadhasivam@...aro.org>, <robh@...nel.org>,
        <krzk+dt@...nel.org>, <conor+dt@...nel.org>, <vkoul@...nel.org>,
        <kishon@...nel.org>, <andersson@...nel.org>, <konradybcio@...nel.org>,
        <p.zabel@...gutronix.de>, <dmitry.baryshkov@...aro.org>,
        <quic_nsekar@...cinc.com>, <linux-arm-msm@...r.kernel.org>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-phy@...ts.infradead.org>,
        Praveenkumar I <quic_ipkumar@...cinc.com>,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v9 6/7] arm64: dts: qcom: ipq5332: Add PCIe related nodes

On Mon, Feb 03, 2025 at 05:30:32PM +0100, Krzysztof Kozlowski wrote:
> On 28/01/2025 07:27, Varadarajan Narayanan wrote:
> >
> > @@ -479,6 +519,230 @@ frame@...8000 {
> >  				status = "disabled";
> >  			};
> >  		};
> > +
> > +		pcie1: pcie@...00000 {
> > +			compatible = "qcom,pcie-ipq5332", "qcom,pcie-ipq9574";
> > +			reg = <0x00088000 0x3000>,
>
> So as Konrad pointed out now, this was never tested. It's not we who
> should run tests for you. It's you.

This was tested and it did not flag an error since it is having the order
specified in the bindings. qcom,pcie.yaml has 4 reg specifications. Two of
them have 'dbi' as the first register space and two of them have 'parf' as
the first register space. Looks like the constraints with 'dbi' as the
first entry will match with pcie@xxx and the ones with 'parf' won't match.

Since IPQ5332 follows the constraints specified for sdx55 which has 'parf'
as the first entry it is not able to match with pcie@xxx value.

The initial version that was posted has the first 'reg' entry matching with
pcie@xxx (please see [1]), since it used the ipq9574 reg constraints. Based
on the feedback received [2], had to add 'mhi' area also. Since adding
'mhi' to ipq9574 would result in duplication of the sdx55 reg constraints,
ipq5332 followed sdx55's constraints resulting in the reg entries getting
reordered and the first reg entry vs pcie@xxx mismatch happened.

To resolve this, shall I reorder the sdx55 reg bindings (and the affected
DTS arch/arm/boot/dts/qcom/qcom-sdx55.dtsi). Please let me know.

1 - https://lore.kernel.org/linux-arm-msm/20241204113329.3195627-6-quic_varada@quicinc.com/
2 - https://lore.kernel.org/linux-arm-msm/6fe09de4-c94c-495d-92a4-aa902d2519ef@oss.qualcomm.com/

> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check W=1` (see
> Documentation/devicetree/bindings/writing-schema.rst or
> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
> for instructions).
> Maybe you need to update your dtschema and yamllint. Don't rely on
> distro packages for dtschema and be sure you are using the latest
> released dtschema.

I run the following tests before posting the patches and go through the
output to see if the nodes I added/changed have any errors or if other dtbs
have been impacted by my bindings changes.

	export ARCH=arm64
	export W=1
	export DT_CHECKER_FLAGS='-v -m'
	export DT_SCHEMA_FILES=qcom
	export CHECK_DTBS=y

	pip3 install dtschema --upgrade

	make -j 16 dt_binding_check

	make -j 16 dtbs_check

	$ pip show dtschema | grep Version
	Version: 2024.11

Please let me know if I should add anything else to ensure my setup is up
to speed.

Thanks
Varada

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