linux-kernel - Re: [PATCH] arm64: dts: renesas: r9a08g045: Add OPP table

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Message-ID: <CAMuHMdUQm0Mk3C7YC+kquXP6qR3-uEYbvhzfJJfL2EZeDosz7g@mail.gmail.com>
Date: Thu, 6 Feb 2025 09:26:50 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Claudiu <claudiu.beznea@...on.dev>
Cc: magnus.damm@...il.com, robh@...nel.org, krzk+dt@...nel.org, 
	conor+dt@...nel.org, linux-renesas-soc@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>, Lukasz Luba <lukasz.luba@....com>, 
	"Rafael J. Wysocki" <rafael@...nel.org>, Linux PM list <linux-pm@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: renesas: r9a08g045: Add OPP table

Hi Claudiu,

CC Energy Model

On Tue, 28 Jan 2025 at 15:56, Claudiu <claudiu.beznea@...on.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>
> Add OPP table for the Renesas RZ/G3S SoC.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
> @@ -28,6 +28,33 @@ audio_clk2: audio2-clk {
>                 clock-frequency = <0>;
>         };
>
> +       cluster0_opp: opp-table-0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-137500000 {
> +                       opp-hz = /bits/ 64 <137500000>;
> +                       opp-microvolt = <940000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-275000000 {
> +                       opp-hz = /bits/ 64 <275000000>;
> +                       opp-microvolt = <940000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-550000000 {
> +                       opp-hz = /bits/ 64 <550000000>;
> +                       opp-microvolt = <940000>;
> +                       clock-latency-ns = <300000>;
> +               };
> +               opp-1100000000 {
> +                       opp-hz = /bits/ 64 <1100000000>;
> +                       opp-microvolt = <940000>;
> +                       clock-latency-ns = <300000>;
> +                       opp-suspend;
> +               };

So all voltages are the same.  This means the Energy Model (if enabled)
will always pick the operating point with the highest clock rate, just
like on R-Car E3 and RZ/G2E.  Apparently that can be fixed by using
"opp-microwatt" instead, but I am still waiting for feedback about
some practical points[1] (yes, the Ebisu-4D is still on my desk for
this reason, and thus unavailable for remote access).

Thanks!

> +       };
> +
>         cpus {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> @@ -40,6 +67,7 @@ cpu0: cpu@0 {
>                         next-level-cache = <&L3_CA55>;
>                         enable-method = "psci";
>                         clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
> +                       operating-points-v2 = <&cluster0_opp>;
>                 };
>
>                 L3_CA55: cache-controller-0 {

[1] https://lore.kernel.org/linux-renesas-soc/cover.1728377971.git.geert+renesas@glider.be

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds