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Message-ID: <173883997042.679546.13069476307207799965.b4-ty@sntech.de>
Date: Thu, 6 Feb 2025 12:06:17 +0100
From: Heiko Stuebner <heiko@...ech.de>
To: Sandy Huang <hjc@...k-chips.com>,
Andy Yan <andy.yan@...k-chips.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Cristian Ciocaltea <cristian.ciocaltea@...labora.com>
Cc: Heiko Stuebner <heiko@...ech.de>,
kernel@...labora.com,
dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
FUKAUMI Naoki <naoki@...xa.com>
Subject: Re: (subset) [PATCH v3 0/5] Improve Rockchip VOP2 display modes handling on RK3588 HDMI0
On Tue, 04 Feb 2025 14:40:03 +0200, Cristian Ciocaltea wrote:
> VOP2 support for RK3588 SoC is currently not capable to handle the full
> range of display modes advertised by the connected screens, e.g. it
> doesn't cope well with non-integer refresh rates like 59.94, 29.97,
> 23.98, etc.
>
> There are two HDMI PHYs available on RK3588, each providing a PLL that
> can be used by three out of the four VOP2 video ports as an alternative
> and more accurate pixel clock source. They are able to handle display
> modes up to 4K@...z, anything above that, e.g. the maximum supported
> 8K@...z resolution, is supposed to be handled by the system CRU.
>
> [...]
Applied, thanks!
[4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
commit: d0f17738778c12be629ba77ff00c43c3e9eb8428
[5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
commit: eb4262203d7d85eb7b6f2696816db272e41f5464
Best regards,
--
Heiko Stuebner <heiko@...ech.de>
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