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Message-ID: <6749f386-4bd0-4395-9ad4-a9663fac9bc1@amd.com>
Date: Fri, 7 Feb 2025 13:08:35 -0600
From: "Bowman, Terry" <terry.bowman@....com>
To: Gregory Price <gourry@...rry.net>
Cc: linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, nifan.cxl@...il.com, dave@...olabs.net,
jonathan.cameron@...wei.com, dave.jiang@...el.com,
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dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
rrichter@....com, nathan.fontenot@....com,
Smita.KoralahalliChannabasappa@....com, lukas@...ner.de,
ming.li@...omail.com, PradeepVineshReddy.Kodamati@....com, alucerop@....com
Subject: Re: [PATCH v5 08/16] cxl/pci: Map CXL PCIe Root Port and Downstream
Switch Port RAS registers
On 2/7/2025 1:30 AM, Gregory Price wrote:
> On Tue, Jan 07, 2025 at 08:38:44AM -0600, Terry Bowman wrote:
>> +static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type)
>> +{
>> + struct pci_dev *pdev;
>> +
>> + if (!dev || !dev_is_pci(dev))
>> + return false;
>> +
>> + pdev = to_pci_dev(dev);
>> +
>> + return (pci_pcie_type(pdev) == pcie_type);
>> +}
>> +
>> +static void cxl_init_ep_ports_aer(struct cxl_ep *ep)
>> +{
>> + struct cxl_dport *dport = ep->dport;
>> +
>> + if (dport) {
>> + struct device *dport_dev = dport->dport_dev;
>> +
>> + if (dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_DOWNSTREAM) ||
>> + dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT))
> Mostly an observation - this kind of comparison seems to be coming up
> more. Wonder if an explicit set of APIs for these checks would be worth
> it to clean up the 3 or 4 different comparison variants i've seen.
>
> Either way
>
> Reviewed-by: Gregory Price <gourry@...rry.net>
>
> ~Gregory
Do you recommend moving dev_is_cxl_pci() to pci library as is? Thanks for 'Reviewed-by:`. Terry
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