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Message-Id: <20250207212954.934-1-rafael.v.volkmer@gmail.com>
Date: Fri, 7 Feb 2025 18:29:54 -0300
From: "Rafael V. Volkmer" <rafael.v.volkmer@...il.com>
To: ukleinek@...nel.org
Cc: linux-kernel@...r.kernel.org,
linux-pwm@...r.kernel.org,
rafael.v.volkmer@...il.com
Subject: [PATCH v3 1/3] pwm: tiehrpwm: replace manual bit definitions with bitfield.h macros
Simplify bit manipulation by replacing manual BIT(x) definitions with
GENMASK() and FIELD_PREP() from <linux/bitfield.h>. This improves
readability, consistency, and aligns with modern kernel practices
while preserving existing functionality.
Additionally, update set_prescale_div() to use FIELD_PREP() for
TBCTL_CLKDIV_MASK and TBCTL_HSPCLKDIV_MASK instead of manually
shifting bits. This makes the code more maintainable and avoids
potential errors in bit field assignments.
Signed-off-by: Rafael V. Volkmer <rafael.v.volkmer@...il.com>
---
drivers/pwm/pwm-tiehrpwm.c | 222 ++++++++++++++++++++++++-------------
1 file changed, 142 insertions(+), 80 deletions(-)
diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c
index 0125e73b98df..50516f46ab04 100644
--- a/drivers/pwm/pwm-tiehrpwm.c
+++ b/drivers/pwm/pwm-tiehrpwm.c
@@ -13,85 +13,147 @@
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
+#include <linux/bitfield.h>
-/* EHRPWM registers and bits definitions */
-
-/* Time base module registers */
-#define TBCTL 0x00
-#define TBPRD 0x0A
-
-#define TBCTL_PRDLD_MASK BIT(3)
-#define TBCTL_PRDLD_SHDW 0
-#define TBCTL_PRDLD_IMDT BIT(3)
-#define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
- BIT(8) | BIT(7))
-#define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
-#define TBCTL_CTRMODE_UP 0
-#define TBCTL_CTRMODE_DOWN BIT(0)
-#define TBCTL_CTRMODE_UPDOWN BIT(1)
-#define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
-
-#define TBCTL_HSPCLKDIV_SHIFT 7
-#define TBCTL_CLKDIV_SHIFT 10
-
-#define CLKDIV_MAX 7
-#define HSPCLKDIV_MAX 7
-#define PERIOD_MAX 0xFFFF
-
-/* compare module registers */
-#define CMPA 0x12
-#define CMPB 0x14
-
-/* Action qualifier module registers */
-#define AQCTLA 0x16
-#define AQCTLB 0x18
-#define AQSFRC 0x1A
-#define AQCSFRC 0x1C
-
-#define AQCTL_CBU_MASK (BIT(9) | BIT(8))
-#define AQCTL_CBU_FRCLOW BIT(8)
-#define AQCTL_CBU_FRCHIGH BIT(9)
-#define AQCTL_CBU_FRCTOGGLE (BIT(9) | BIT(8))
-#define AQCTL_CAU_MASK (BIT(5) | BIT(4))
-#define AQCTL_CAU_FRCLOW BIT(4)
-#define AQCTL_CAU_FRCHIGH BIT(5)
-#define AQCTL_CAU_FRCTOGGLE (BIT(5) | BIT(4))
-#define AQCTL_PRD_MASK (BIT(3) | BIT(2))
-#define AQCTL_PRD_FRCLOW BIT(2)
-#define AQCTL_PRD_FRCHIGH BIT(3)
-#define AQCTL_PRD_FRCTOGGLE (BIT(3) | BIT(2))
-#define AQCTL_ZRO_MASK (BIT(1) | BIT(0))
-#define AQCTL_ZRO_FRCLOW BIT(0)
-#define AQCTL_ZRO_FRCHIGH BIT(1)
-#define AQCTL_ZRO_FRCTOGGLE (BIT(1) | BIT(0))
-
-#define AQCTL_CHANA_POLNORMAL (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | \
- AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANA_POLINVERSED (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | \
- AQCTL_ZRO_FRCLOW)
-#define AQCTL_CHANB_POLNORMAL (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | \
- AQCTL_ZRO_FRCHIGH)
-#define AQCTL_CHANB_POLINVERSED (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | \
- AQCTL_ZRO_FRCLOW)
-
-#define AQSFRC_RLDCSF_MASK (BIT(7) | BIT(6))
-#define AQSFRC_RLDCSF_ZRO 0
-#define AQSFRC_RLDCSF_PRD BIT(6)
-#define AQSFRC_RLDCSF_ZROPRD BIT(7)
-#define AQSFRC_RLDCSF_IMDT (BIT(7) | BIT(6))
-
-#define AQCSFRC_CSFB_MASK (BIT(3) | BIT(2))
-#define AQCSFRC_CSFB_FRCDIS 0
-#define AQCSFRC_CSFB_FRCLOW BIT(2)
-#define AQCSFRC_CSFB_FRCHIGH BIT(3)
-#define AQCSFRC_CSFB_DISSWFRC (BIT(3) | BIT(2))
-#define AQCSFRC_CSFA_MASK (BIT(1) | BIT(0))
-#define AQCSFRC_CSFA_FRCDIS 0
-#define AQCSFRC_CSFA_FRCLOW BIT(0)
-#define AQCSFRC_CSFA_FRCHIGH BIT(1)
-#define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0))
-
-#define NUM_PWM_CHANNEL 2 /* EHRPWM channels */
+/*
+ * --------------------------------------
+ * Time base module registers
+ * --------------------------------------
+ */
+#define TBCTL 0x00
+#define TBPRD 0x0A
+
+/* TBCTL: CTRMODE field (bits [1:0]) */
+#define TBCTL_CTRMODE_MASK GENMASK(1, 0)
+
+/* The possible values for that field */
+#define TBCTL_CTRMODE_UP FIELD_PREP(TBCTL_CTRMODE_MASK, 0U)
+#define TBCTL_CTRMODE_DOWN FIELD_PREP(TBCTL_CTRMODE_MASK, 1U)
+#define TBCTL_CTRMODE_UPDOWN FIELD_PREP(TBCTL_CTRMODE_MASK, 2U)
+#define TBCTL_CTRMODE_FREEZE FIELD_PREP(TBCTL_CTRMODE_MASK, 3U)
+
+/* TBCTL: PRDLD bit (bit [3]) */
+#define TBCTL_PRDLD_MASK GENMASK(3, 3)
+
+/* Possible values for PRDLD */
+#define TBCTL_PRDLD_SHDW FIELD_PREP(TBCTL_PRDLD_MASK, 0U) /* 0 => shadow */
+#define TBCTL_PRDLD_IMDT FIELD_PREP(TBCTL_PRDLD_MASK, 1U) /* 1 => immediate */
+
+/* TBCTL: Combined bits [12:7] actually split into two subfields:
+ * - TBCTL_HSPCLKDIV => bits [9:7]
+ * - TBCTL_CLKDIV => bits [12:10]
+ */
+#define TBCTL_HSPCLKDIV_MASK GENMASK(9, 7)
+#define TBCTL_CLKDIV_MASK GENMASK(12, 10)
+
+/* Max values if needed: */
+#define CLKDIV_MAX 7U
+#define HSPCLKDIV_MAX 7U
+#define PERIOD_MAX 0xFFFF
+
+/*
+ * --------------------------------------
+ * Compare module registers
+ * --------------------------------------
+ */
+#define CMPA 0x12
+#define CMPB 0x14
+
+/*
+ * --------------------------------------
+ * Action qualifier (AQ) module registers
+ * --------------------------------------
+ */
+#define AQCTLA 0x16
+#define AQCTLB 0x18
+#define AQSFRC 0x1A
+#define AQCSFRC 0x1C
+
+/*
+ * AQCTLA and AQCTLB share similar 2-bit fields for
+ * various events (ZRO, PRD, CAU, CBU, etc.).
+ *
+ * For instance, bits [1:0] => ZRO,
+ * bits [3:2] => PRD,
+ * bits [5:4] => CAU,
+ * bits [9:8] => CBU, etc.
+ */
+#define AQCTL_ZRO_MASK GENMASK(1, 0)
+#define AQCTL_PRD_MASK GENMASK(3, 2)
+#define AQCTL_CAU_MASK GENMASK(5, 4)
+#define AQCTL_CBU_MASK GENMASK(9, 8)
+
+/*
+ * FORCE LOW => 0b01
+ * FORCE HIGH => 0b01
+ * FORCE TOGGLE => 0b01
+ */
+#define AQCTL_FRCLOW 1U
+#define AQCTL_FRCHIGH 2U
+#define AQCTL_FRCTOGGLE 3U
+
+/* These values in CAU: */
+#define AQCTL_CAU_FRCLOW FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CAU_FRCHIGH FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CAU_FRCTOGGLE FIELD_PREP(AQCTL_CAU_MASK, AQCTL_FRCTOGGLE)
+
+/* These values in PRD: */
+#define AQCTL_PRD_FRCLOW FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCLOW)
+#define AQCTL_PRD_FRCHIGH FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCHIGH)
+#define AQCTL_PRD_FRCTOGGLE FIELD_PREP(AQCTL_PRD_MASK, AQCTL_FRCTOGGLE)
+
+/* These values in ZRO: */
+#define AQCTL_ZRO_FRCLOW FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCLOW)
+#define AQCTL_ZRO_FRCHIGH FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCHIGH)
+#define AQCTL_ZRO_FRCTOGGLE FIELD_PREP(AQCTL_ZRO_MASK, AQCTL_FRCTOGGLE)
+
+/* These values in CBU: */
+#define AQCTL_CBU_FRCLOW FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCLOW)
+#define AQCTL_CBU_FRCHIGH FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCHIGH)
+#define AQCTL_CBU_FRCTOGGLE FIELD_PREP(AQCTL_CBU_MASK, AQCTL_FRCTOGGLE)
+
+/* Predefined combinations for channel polarity */
+#define AQCTL_CHANA_POLNORMAL \
+ (AQCTL_CAU_FRCLOW | AQCTL_PRD_FRCHIGH | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHANA_POLINVERSED \
+ (AQCTL_CAU_FRCHIGH | AQCTL_PRD_FRCLOW | AQCTL_ZRO_FRCLOW)
+#define AQCTL_CHANB_POLNORMAL \
+ (AQCTL_CBU_FRCLOW | AQCTL_PRD_FRCHIGH | AQCTL_ZRO_FRCHIGH)
+#define AQCTL_CHANB_POLINVERSED \
+ (AQCTL_CBU_FRCHIGH | AQCTL_PRD_FRCLOW | AQCTL_ZRO_FRCLOW)
+
+/* AQSFRC: RLDCSF => bits [7:6] */
+#define AQSFRC_RLDCSF_MASK GENMASK(7, 6)
+
+#define AQSFRC_RLDCSF_ZRO FIELD_PREP(AQSFRC_RLDCSF_MASK, 0U)
+#define AQSFRC_RLDCSF_PRD FIELD_PREP(AQSFRC_RLDCSF_MASK, 1U)
+#define AQSFRC_RLDCSF_ZROPRD FIELD_PREP(AQSFRC_RLDCSF_MASK, 2U)
+#define AQSFRC_RLDCSF_IMDT FIELD_PREP(AQSFRC_RLDCSF_MASK, 3U)
+
+/* AQCSFRC: CSFB => bits [3:2], CSFA => bits [1:0] */
+#define AQCSFRC_CSFB_MASK GENMASK(3, 2)
+#define AQCSFRC_CSFA_MASK GENMASK(1, 0)
+
+/* The possible 2-bit values for CSFB or CSFA fields */
+#define AQCSFRC_FRCDIS 0U
+#define AQCSFRC_FRCLOW 1U
+#define AQCSFRC_FRCHIGH 2U
+#define AQCSFRC_DISSWFRC 3U
+
+/* These values in CSFB: */
+#define AQCSFRC_CSFB_FRCDIS FIELD_PREP(AQCSFRC_CSFB_MASK, AQCSFRC_FRCDIS)
+#define AQCSFRC_CSFB_FRCLOW FIELD_PREP(AQCSFRC_CSFB_MASK, AQCSFRC_FRCLOW)
+#define AQCSFRC_CSFB_FRCHIGH FIELD_PREP(AQCSFRC_CSFB_MASK, AQCSFRC_FRCHIGH)
+#define AQCSFRC_CSFB_DISSWFRC FIELD_PREP(AQCSFRC_CSFB_MASK, AQCSFRC_DISSWFRC)
+
+/* These values in CSFA: */
+#define AQCSFRC_CSFA_FRCDIS FIELD_PREP(AQCSFRC_CSFA_MASK, AQCSFRC_FRCDIS)
+#define AQCSFRC_CSFA_FRCLOW FIELD_PREP(AQCSFRC_CSFA_MASK, AQCSFRC_FRCLOW)
+#define AQCSFRC_CSFA_FRCHIGH FIELD_PREP(AQCSFRC_CSFA_MASK, AQCSFRC_FRCHIGH)
+#define AQCSFRC_CSFA_DISSWFRC FIELD_PREP(AQCSFRC_CSFA_MASK, AQCSFRC_DISSWFRC)
+
+/* EHRPWM channels */
+#define NUM_PWM_CHANNEL 2U
struct ehrpwm_context {
u16 tbctl;
@@ -167,8 +229,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div,
*prescale_div = (1 << clkdiv) *
(hspclkdiv ? (hspclkdiv * 2) : 1);
if (*prescale_div > rqst_prescaler) {
- *tb_clk_div = (clkdiv << TBCTL_CLKDIV_SHIFT) |
- (hspclkdiv << TBCTL_HSPCLKDIV_SHIFT);
+ *tb_clk_div = FIELD_PREP(TBCTL_CLKDIV_MASK, clkdiv) |
+ FIELD_PREP(TBCTL_HSPCLKDIV_MASK, hspclkdiv);
return 0;
}
}
--
2.25.1
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