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Message-ID: <db2ec4cb-9769-4d76-a8a3-308c83d77602@quicinc.com>
Date: Thu, 6 Feb 2025 17:12:22 -0800
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Jun Nie <jun.nie@...aro.org>, Rob Clark <robdclark@...il.com>,
"Abhinav
Kumar" <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov
<dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Simona
Vetter" <simona@...ll.ch>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 02/15] drm/msm/dpu: Do not fix number of DSC
On 1/17/2025 8:00 AM, Jun Nie wrote:
> Currently, if DSC is enabled, only 2 DSC engines are supported so far.
> More usage cases will be added, such as 4 DSC in 4:4:2 topology. So
> get the real number of DSCs to decide whether DSC merging is needed.
>
> Signed-off-by: Jun Nie <jun.nie@...aro.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@...cinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index eaac172141ede..c734d2c5790d2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -164,6 +164,7 @@ enum dpu_enc_rc_states {
> * clks and resources after IDLE_TIMEOUT time.
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> + * @num_dscs: Number of DSCs in use
> * @wide_bus_en: wide bus is enabled on this interface
> * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
> */
> @@ -204,6 +205,7 @@ struct dpu_encoder_virt {
> struct msm_display_topology topology;
>
> u32 idle_timeout;
> + u32 num_dscs;
>
> bool wide_bus_en;
>
> @@ -622,9 +624,8 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc)
> if (dpu_enc->phys_encs[i])
> intf_count++;
>
> - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */
> if (dpu_enc->dsc)
> - num_dsc = 2;
> + num_dsc = dpu_enc->num_dscs;
>
> return (num_dsc > 0) && (num_dsc > intf_count);
> }
> @@ -1261,6 +1262,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> }
>
> + dpu_enc->num_dscs = num_dsc;
> dpu_enc->dsc_mask = dsc_mask;
>
> if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) ||
>
> --
> 2.34.1
>
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