linux-kernel - [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions

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Message-Id: <20250207083616.1442887-6-alexander.stein@ew.tq-group.com>
Date: Fri,  7 Feb 2025 09:36:10 +0100
From: Alexander Stein <alexander.stein@...tq-group.com>
To: Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	Srinivas Kandagatla <srinivas.kandagatla@...aro.org>
Cc: Alexander Stein <alexander.stein@...tq-group.com>,
	devicetree@...r.kernel.org,
	imx@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH v2 05/10] arm64: dts: imx8mp: Add i.MX8M Plus OCOTP disable fuse definitions

These definitions define the location of corresponding disable bits
in OCOTP peripheral.

Signed-off-by: Alexander Stein <alexander.stein@...tq-group.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-ocotp.h | 42 ++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-ocotp.h

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
new file mode 100644
index 0000000000000..c9f49c61f3656
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ocotp.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (c) 2025 TQ-Systems GmbH <linux@...tq-group.com>,
+ * D-82229 Seefeld, Germany.
+ * Author: Alexander Stein
+ */
+
+#ifndef __DTS_IMX8MP_OCOTP_H
+#define __DTS_IMX8MP_OCOTP_H
+
+/*
+ * The OCOTP is a tuple of
+ * <fuse_addr fuse_bit_offset>
+ */
+
+#define IMX8MP_OCOTP_M7_DISABLE			16 21
+#define IMX8MP_OCOTP_VPU_G1_DISABLE		16 24
+#define IMX8MP_OCOTP_VPU_G2_DISABLE		16 25
+#define IMX8MP_OCOTP_CAN_DISABLE		16 28
+#define IMX8MP_OCOTP_CAN_FD_DISABLE		16 29
+#define IMX8MP_OCOTP_VPU_VC8000E_DISABLE	16 30
+#define IMX8MP_OCOTP_IMG_ISP1_DISABLE		20 0
+#define IMX8MP_OCOTP_IMG_ISP2_DISABLE		20 1
+#define IMX8MP_OCOTP_IMG_DEWARP_DISABLE		20 2
+#define IMX8MP_OCOTP_NPU_DISABLE		20 3
+#define IMX8MP_OCOTP_AUDIO_PROCESSOR_DISABLE	20 4
+#define IMX8MP_OCOTP_ASRC_DISABLE		20 5
+#define IMX8MP_OCOTP_GPU2_DISABLE		20 6
+#define IMX8MP_OCOTP_GPU3_DISABLE		20 7
+#define IMX8MP_OCOTP_USB1_DISABLE		20 8
+#define IMX8MP_OCOTP_USB2_DISABLE		20 9
+#define IMX8MP_OCOTP_PCIE1_DISABLE		20 11
+#define IMX8MP_OCOTP_ENET1_DISABLE		20 13
+#define IMX8MP_OCOTP_ENET2_DISABLE		20 14
+#define IMX8MP_OCOTP_MIPI_CSI1_DISABLE		20 15
+#define IMX8MP_OCOTP_MIPI_CSI2_DISABLE		20 16
+#define IMX8MP_OCOTP_MIPI_DSI1_DISABLE		20 17
+#define IMX8MP_OCOTP_LVDS1_DISABLE		20 19
+#define IMX8MP_OCOTP_LVDS2_DISABLE		20 20
+#define IMX8MP_OCOTP_EARC_RX_DISABLE		20 30
+
+#endif /* __DTS_IMX8MP_OCOTP_H */
-- 
2.34.1