linux-kernel - Re: [PATCH 2/2] arm64: dts: qcom: sm8650: add PPI interrupt partitions for the ARM PMUs

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Message-ID: <bbbd36a1-d67c-404c-b749-eefcf493ed7f@oss.qualcomm.com>
Date: Mon, 10 Feb 2025 16:23:58 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: neil.armstrong@...aro.org, Konrad Dybcio
 <konrad.dybcio@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8650: add PPI interrupt
 partitions for the ARM PMUs

On 9.02.2025 3:44 PM, Neil Armstrong wrote:
> On 07/02/2025 21:30, Konrad Dybcio wrote:
>> On 7.02.2025 11:31 AM, Neil Armstrong wrote:
>>> The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
>>> interrupt partition maps and use the 4th interrupt cell to pass the
>>> partition phandle for each ARM PMU node.
>>>
>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>> ---
>>
>>> @@ -5309,6 +5309,20 @@ intc: interrupt-controller@...00000 {
>>>               #size-cells = <2>;
>>>               ranges;
>>>   +            ppi-partitions {
>>> +                ppi_cluster0: interrupt-partition-0 {
>>> +                    affinity = <&cpu0 &cpu1>;
>>> +                };
>>> +
>>> +                ppi_cluster1: interrupt-partition-1 {
>>> +                    affinity = <&cpu2 &cpu3 &cpu4 &cpu5 &cpu6>;
>>> +                };
>>> +
>>> +                ppi_cluster2: interrupt-partition-2 {
>>> +                    affinity = <&cpu7>;
>>> +                };
>>
>> I'm not sure this is accurate.
>>
>> I *think* it's cores 0-1 and 2-7, but I can't find a concrete answer
> 
> Core 7 is a Cortex-X4, and has a dedicated PMU node, look at the cpu compatibles.

Look at what these compatibles do in code. Nothing special for the X.

Konrad