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Message-ID: <Z6pI7oGXYyoecJzG@gourry-fedora-PF4VCD3F>
Date: Mon, 10 Feb 2025 13:43:58 -0500
From: Gregory Price <gourry@...rry.net>
To: Terry Bowman <terry.bowman@....com>
Cc: linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, nifan.cxl@...il.com, dave@...olabs.net,
jonathan.cameron@...wei.com, dave.jiang@...el.com,
alison.schofield@...el.com, vishal.l.verma@...el.com,
dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
rrichter@....com, nathan.fontenot@....com,
Smita.KoralahalliChannabasappa@....com, lukas@...ner.de,
ming.li@...omail.com, PradeepVineshReddy.Kodamati@....com
Subject: Re: [PATCH v6 06/17] PCI/AER: Add CXL PCIe Port uncorrectable error
recovery in AER service driver
On Fri, Feb 07, 2025 at 06:29:30PM -0600, Terry Bowman wrote:
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index a5c65f79db18..eda532f7440c 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -661,10 +661,16 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds,
>
> addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET;
> status = readl(addr);
> - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
> - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> - trace_cxl_aer_correctable_error(cxlds->cxlmd, status);
> + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) {
> + dev_err(cxl_dev, "%s():%d: CE Status is empty\n", __func__, __LINE__);
> + return;
> }
> + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
> +
> + if (is_cxl_memdev(cxl_dev))
> + trace_cxl_aer_correctable_error(to_cxl_memdev(cxl_dev), status);
> + else if (is_cxl_port(cxl_dev))
> + trace_cxl_port_aer_correctable_error(cxl_dev, pcie_dev, status);
^^^^^^^^
Parameter isn't added until patch 14 - causes a build error.
~Gregory
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