[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250210213549.1867704-9-cleger@rivosinc.com>
Date: Mon, 10 Feb 2025 22:35:41 +0100
From: Clément Léger <cleger@...osinc.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Anup Patel <anup@...infault.org>,
Atish Patra <atishp@...shpatra.org>,
Shuah Khan <shuah@...nel.org>,
Jonathan Corbet <corbet@....net>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org,
kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org,
linux-kselftest@...r.kernel.org
Cc: Clément Léger <cleger@...osinc.com>,
Samuel Holland <samuel.holland@...ive.com>
Subject: [PATCH v2 08/15] riscv: misaligned: enable IRQs while handling misaligned accesses
We can safely reenable IRQs if they were enabled in the previous
context. This allows to access user memory that could potentially
trigger a page fault.
Signed-off-by: Clément Léger <cleger@...osinc.com>
---
arch/riscv/kernel/traps.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 55d9f3450398..3eecc2addc41 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -206,6 +206,11 @@ enum misaligned_access_type {
static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type type)
{
irqentry_state_t state = irqentry_enter(regs);
+ bool enable_irqs = !regs_irqs_disabled(regs);
+
+ /* Enable interrupts if they were enabled in the interrupted context. */
+ if (enable_irqs)
+ local_irq_enable();
if (type == MISALIGNED_LOAD) {
if (handle_misaligned_load(regs))
@@ -217,6 +222,9 @@ static void do_trap_misaligned(struct pt_regs *regs, enum misaligned_access_type
"Oops - store (or AMO) address misaligned");
}
+ if (enable_irqs)
+ local_irq_disable();
+
irqentry_exit(regs, state);
}
--
2.47.2
Powered by blists - more mailing lists