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Message-ID: <5ab133b4-0146-0b14-04be-20ef4cfeef1b@quicinc.com>
Date: Mon, 10 Feb 2025 15:07:32 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
CC: Rob Herring <robh@...nel.org>, <andersson@...nel.org>,
Bjorn Helgaas
<bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Konrad Dybcio
<konradybcio@...nel.org>,
<cros-qcom-dts-watchers@...omium.org>,
Jingoo Han
<jingoohan1@...il.com>,
Bartosz Golaszewski <brgl@...ev.pl>, <quic_vbadigan@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/6] dt-bindings: PCI: Add binding for qps615
On 2/10/2025 1:21 PM, Manivannan Sadhasivam wrote:
> On Wed, Dec 04, 2024 at 02:19:56PM +0530, Krishna Chaitanya Chundru wrote:
>
> [...]
>
>>>>> + pcie@3,0 {
>>>>> + reg = <0x21800 0x0 0x0 0x0 0x0>;
>>>>> + #address-cells = <3>;
>>>>> + #size-cells = <2>;
>>>>> + device_type = "pci";
>>>>> + ranges;
>>>>> + bus-range = <0x05 0xff>;
>>>>> +
>>>>> + qcom,tx-amplitude-millivolt = <10>;
>>>>> + pcie@0,0 {
>>>>> + reg = <0x50000 0x0 0x0 0x0 0x0>;
>>>>> + #address-cells = <3>;
>>>>> + #size-cells = <2>;
>>>>> + device_type = "pci";
>>>>
>>>> There's a 2nd PCI-PCI bridge?
>>> This the embedded ethernet port which is as part of DSP3.
>>>
>> Hi Rob,
>>
>> Can you please check my response on your queries, if you need
>> any extra information, we can provide to sort this out.
>>
>
> I believe Rob was pointing the 'device_type' property which is not needed for
> PCI device nodes but only for nodes implementing PCI bus (like host bridge, PCI
> bridge).
>
Got it, I will remove device_type in the next patch series.
- Krishna Chaitanya.
> - Mani
>
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