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Message-ID: <20250211002340.25miqmaafdc52g4q@synopsys.com>
Date: Tue, 11 Feb 2025 00:23:43 +0000
From: Thinh Nguyen <Thinh.Nguyen@...opsys.com>
To: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
CC: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
        Felipe Balbi <balbi@...nel.org>,
        "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Ferry Toth <fntoth@...il.com>
Subject: Re: [PATCH v2 3/3] usb: dwc3: gadget: Avoid using reserved endpoints
 on Intel Merrifield

On Mon, Feb 03, 2025, Andy Shevchenko wrote:
> Intel Merrifield SoC uses these endpoints for tracing and they cannot
> be re-allocated if being used because the side band flow control signals
> are hard wired to certain endpoints:
> 
> • 1 High BW Bulk IN (IN#1) (RTIT)
> • 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8)
> 
> In device mode, since RTIT (EP#1) and EXI/RunControl (EP#8) uses
> External Buffer Control (EBC) mode, these endpoints are to be mapped to
> EBC mode (to be done by EXI target driver). Additionally TRB for RTIT
> and EXI are maintained in STM (System Trace Module) unit and the EXI
> target driver will as well configure the TRB location for EP #1 IN
> and EP#8 (IN and OUT). Since STM/PTI and EXI hardware blocks manage
> these endpoints and interface to OTG3 controller through EBC interface,
> there is no need to enable any events (such as XferComplete etc)
> for these end points.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
> ---
>  drivers/usb/dwc3/dwc3-pci.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
> index 052852f80146..54a4ee2b90b7 100644
> --- a/drivers/usb/dwc3/dwc3-pci.c
> +++ b/drivers/usb/dwc3/dwc3-pci.c
> @@ -148,11 +148,21 @@ static const struct property_entry dwc3_pci_intel_byt_properties[] = {
>  	{}
>  };
>  
> +/*
> + * Intel Merrifield SoC uses these endpoints for tracing and they cannot
> + * be re-allocated if being used because the side band flow control signals
> + * are hard wired to certain endpoints:
> + * - 1 High BW Bulk IN (IN#1) (RTIT)
> + * - 1 1KB BW Bulk IN (IN#8) + 1 1KB BW Bulk OUT (Run Control) (OUT#8)
> + */
> +static const u8 dwc3_pci_mrfld_reserved_endpoints[] = { 3, 16, 17 };
> +
>  static const struct property_entry dwc3_pci_mrfld_properties[] = {
>  	PROPERTY_ENTRY_STRING("dr_mode", "otg"),
>  	PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
>  	PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
>  	PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
> +	PROPERTY_ENTRY_U8_ARRAY("snps,reserved-endpoints", dwc3_pci_mrfld_reserved_endpoints),
>  	PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
>  	PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
>  	{}
> -- 
> 2.43.0.rc1.1336.g36b5255a03ac
> 

Acked-by: Thinh Nguyen <Thinh.Nguyen@...opsys.com>

Thanks,
Thinh

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