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Message-ID: <13f7d30e-9237-4a3e-b9a7-0c667b3e77a8@oss.qualcomm.com>
Date: Tue, 11 Feb 2025 15:36:26 +0100
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>,
        Georgi Djakov <djakov@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley
 <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
Cc: Odelu Kukatla <quic_okukatla@...cinc.com>,
        Mike Tipton <quic_mdtipton@...cinc.com>,
        Jeff Johnson <quic_jjohnson@...cinc.com>,
        Andrew Halaney <ahalaney@...hat.com>,
        Sibi Sankar <quic_sibis@...cinc.com>, linux-arm-msm@...r.kernel.org,
        linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH V8 6/7] arm64: dts: qcom: sa8775p: add EPSS l3
 interconnect provider

On 5.02.2025 7:27 PM, Raviteja Laggyshetty wrote:
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P
> SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs.
> These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for
> programming the perf level. This is taken care in the data associated
> with the target specific compatible. Since, the HW is same in the all
> SoCs with EPSS support, using the same generic compatible for all.
> 
> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@...cinc.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>

Konrad

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