linux-kernel - [PATCH v6 0/7] Add PCIe Root Port support for Agilex family of chips

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-Id: <20250211151725.4133582-1-matthew.gerlach@linux.intel.com>
Date: Tue, 11 Feb 2025 09:17:18 -0600
From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
To: lpieralisi@...nel.org,
	kw@...ux.com,
	manivannan.sadhasivam@...aro.org,
	robh@...nel.org,
	bhelgaas@...gle.com,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	dinguyen@...nel.org,
	joyce.ooi@...el.com,
	linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: matthew.gerlach@...era.com,
	peter.colberg@...era.com,
	Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v6 0/7] Add PCIe Root Port support for Agilex family of chips

This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.
Version 6 refactors duplicate dts snippets into dtsi's for correctness and
maintainability.

Patch 1:
  Add new compatible strings for the three variants of the Agilex PCIe controller IP.

Patch 2:
  Fix fixed-clock schema warnings in socfpga_agilex.dtsi before adding to it.

Patch 3:
  Move bus@...00000 dt node to socfpga_agilex.dtsi.

Patch 4:
  Refactor duplicate dts into dtsi.

Patch 5:
  Add base dtsi for PCIe Root Port support of the Agilex family of chips.

Patch 6:
  Add dts enabling PCIe Root Port support on an Agilex F-series Development Kit.

Patch 7:
  Update Altera PCIe controller driver to support the Agilex family of chips.

D M, Sharath Kumar (1):
  PCI: altera: Add Agilex support

Matthew Gerlach (6):
  dt-bindings: PCI: altera: Add binding for Agilex
  arm64: dts: agilex: Fix fixed-clock schema warnings
  arm64: dts: agilex: move bus@...00000 to socfpga_agilex.dtsi
  arm64: dts: agilex: refactor shared dts into dtsi
  arm64: dts: agilex: add dtsi for PCIe Root Port
  arm64: dts: agilex: add dts enabling PCIe Root Port

 .../bindings/pci/altr,pcie-root-port.yaml     |  10 +
 arch/arm64/boot/dts/intel/Makefile            |   1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  14 +
 .../socfpga_agilex7f_socdk_pcie_root_port.dts |  87 ++++++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   |  28 +-
 .../intel/socfpga_agilex_pcie_root_port.dtsi  |  48 ++++
 .../boot/dts/intel/socfpga_agilex_socdk.dts   |  62 +----
 .../boot/dts/intel/socfpga_agilex_socdk.dtsi  |  65 +++++
 .../dts/intel/socfpga_agilex_socdk_nand.dts   |  62 +----
 drivers/pci/controller/pcie-altera.c          | 253 +++++++++++++++++-
 10 files changed, 481 insertions(+), 149 deletions(-)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi

-- 
2.34.1