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Message-Id: <20250211151725.4133582-5-matthew.gerlach@linux.intel.com>
Date: Tue, 11 Feb 2025 09:17:22 -0600
From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
To: lpieralisi@...nel.org,
kw@...ux.com,
manivannan.sadhasivam@...aro.org,
robh@...nel.org,
bhelgaas@...gle.com,
krzk+dt@...nel.org,
conor+dt@...nel.org,
dinguyen@...nel.org,
joyce.ooi@...el.com,
linux-pci@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: matthew.gerlach@...era.com,
peter.colberg@...era.com,
Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v6 4/7] arm64: dts: agilex: refactor shared dts into dtsi
Move common device tree from socfpga_agilex_socdk*.dts to
socfpga_agilex_socdk.dtsi.
Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
---
v6:
- New patch to series.
---
.../boot/dts/intel/socfpga_agilex_socdk.dts | 62 +-----------------
.../boot/dts/intel/socfpga_agilex_socdk.dtsi | 65 +++++++++++++++++++
.../dts/intel/socfpga_agilex_socdk_nand.dts | 62 +-----------------
3 files changed, 67 insertions(+), 122 deletions(-)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..a970f612333a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -3,50 +3,7 @@
* Copyright (C) 2019, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
-
-/ {
- model = "SoCFPGA Agilex SoCDK";
- compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "hps_led0";
- gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
- };
-
- led1 {
- label = "hps_led1";
- gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
- };
-
- led2 {
- label = "hps_led2";
- gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@...00000 {
- device_type = "memory";
- /* We expect the bootloader to fill in the reg */
- reg = <0 0x80000000 0 0>;
- };
-};
-
-&gpio1 {
- status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
&gmac0 {
status = "okay";
@@ -86,23 +43,6 @@ &mmc {
clk-phase-sd-hs = <0>, <135>;
};
-&osc1 {
- clock-frequency = <25000000>;
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- disable-over-current;
-};
-
-&watchdog0 {
- status = "okay";
-};
-
&qspi {
status = "okay";
flash@0 {
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
new file mode 100644
index 000000000000..e0f3ff60aa33
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019, Intel Corporation
+ */
+
+/ {
+ model = "SoCFPGA Agilex SoCDK";
+ compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0x80000000 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
index 0f9020bd0c52..53a533cd2789 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts
@@ -3,50 +3,7 @@
* Copyright (C) 2019, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
-
-/ {
- model = "SoCFPGA Agilex SoCDK";
- compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex";
-
- aliases {
- serial0 = &uart0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
- ethernet2 = &gmac2;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- led0 {
- label = "hps_led0";
- gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
- };
-
- led1 {
- label = "hps_led1";
- gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
- };
-
- led2 {
- label = "hps_led2";
- gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
- };
- };
-
- memory@...00000 {
- device_type = "memory";
- /* We expect the bootloader to fill in the reg */
- reg = <0 0x80000000 0 0>;
- };
-};
-
-&gpio1 {
- status = "okay";
-};
+#include "socfpga_agilex_socdk.dtsi"
&gmac2 {
status = "okay";
@@ -97,20 +54,3 @@ partition@...000 {
};
};
};
-
-&osc1 {
- clock-frequency = <25000000>;
-};
-
-&uart0 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- disable-over-current;
-};
-
-&watchdog0 {
- status = "okay";
-};
--
2.34.1
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