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Message-ID: <20250211185114.GA51552@bhelgaas>
Date: Tue, 11 Feb 2025 12:51:14 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Thippeswamy Havalige <thippeswamy.havalige@....com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
	manivannan.sadhasivam@...aro.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	michal.simek@....com, bharat.kumar.gogada@....com
Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC
 Root Port controller

On Tue, Feb 11, 2025 at 01:47:24PM +0530, Thippeswamy Havalige wrote:
> The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> incorporate the Coherency and PCIe Gen5 Module, specifically the
> Next-Generation Compact Module (CPM5NC).
> 
> The integrated CPM5NC block, along with the built-in bridge, can function
> as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> configuration.
> 
> Bridge errors are managed using a specific interrupt line designed for
> CPM5N. Legacy interrupt support is not available.

I guess this means INTx support is not available?

If so, I'd like to say "INTx" instead of "legacy" to be more specific.
Someday "MSI" may also be considered "legacy".

Bjorn

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