linux-kernel - [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

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Message-ID: <20250211025317.399534-6-sunny.shen@mediatek.com>
Date: Tue, 11 Feb 2025 10:52:54 +0800
From: Sunny Shen <sunny.shen@...iatek.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Chun-Kuang Hu <chunkuang.hu@...nel.org>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
CC: Matthias Brugger <matthias.bgg@...il.com>, Philipp Zabel
	<p.zabel@...gutronix.de>, Fei Shao <fshao@...omium.org>, Pin-yen Lin
	<treapking@...omium.org>, "Jason-JH . Lin" <jason-jh.lin@...iatek.com>, Nancy
 Lin <nancy.lin@...iatek.com>, Singo Chang <singo.chang@...iatek.com>, "Paul
 Chen --cc=devicetree @ vger . kernel . org" <paul-pl.chen@...iatek.com>,
	<linux-kernel@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
	<linux-mediatek@...ts.infradead.org>, <linux-arm-kernel@...ts.infradead.org>,
	<Project_Global_Chrome_Upstream_Group@...iatek.com>, Sunny Shen
	<sunny.shen@...iatek.com>
Subject: [PATCH 5/5] drm/mediatek: Change main display path to support PQ for MT8196

Due to the path mux design of the MT8196, the following components
need to be added to support Picture Quality (PQ) in the main display
path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0.

Signed-off-by: Sunny Shen <sunny.shen@...iatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b810a197f58b..1c97dc46ae70 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = {
 
 static const unsigned int mt8196_mtk_ddp_disp0_main[] = {
 	DDP_COMPONENT_DLI_ASYNC0,
+	DDP_COMPONENT_MDP_RSZ0,
+	DDP_COMPONENT_TDSHP0,
+	DDP_COMPONENT_CCORR0,
+	DDP_COMPONENT_CCORR1,
+	DDP_COMPONENT_GAMMA0,
+	DDP_COMPONENT_POSTMASK0,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DLO_ASYNC1,
 };
 
-- 
2.34.1