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Message-ID: <66346ce9-8b75-4642-a755-22591188784f@amd.com>
Date: Tue, 11 Feb 2025 11:16:47 +0530
From: Dhananjay Ugwekar <Dhananjay.Ugwekar@....com>
To: Mario Limonciello <superm1@...nel.org>,
 "Gautham R . Shenoy" <gautham.shenoy@....com>,
 Perry Yuan <perry.yuan@....com>
Cc: "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
 <linux-kernel@...r.kernel.org>,
 "open list:CPU FREQUENCY SCALING FRAMEWORK" <linux-pm@...r.kernel.org>,
 Mario Limonciello <mario.limonciello@....com>
Subject: Re: [PATCH 05/14] cpufreq/amd-pstate: Drop `cppc_cap1_cached`

On 2/7/2025 3:26 AM, Mario Limonciello wrote:
> From: Mario Limonciello <mario.limonciello@....com>
> 
> The `cppc_cap1_cached` variable isn't used at all, there is no
> need to read it at initialization for each CPU.

Looks good to me,

Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@....com>

Thanks,
Dhananjay

> 
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  drivers/cpufreq/amd-pstate.c | 5 -----
>  drivers/cpufreq/amd-pstate.h | 2 --
>  2 files changed, 7 deletions(-)
> 
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index dd230ed3b9579..71636bd9884c8 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1529,11 +1529,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
>  		if (ret)
>  			return ret;
>  		WRITE_ONCE(cpudata->cppc_req_cached, value);
> -
> -		ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value);
> -		if (ret)
> -			return ret;
> -		WRITE_ONCE(cpudata->cppc_cap1_cached, value);
>  	}
>  	ret = amd_pstate_set_epp(cpudata, cpudata->epp_default);
>  	if (ret)
> diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h
> index 6d776c3e5712a..7501d30db9953 100644
> --- a/drivers/cpufreq/amd-pstate.h
> +++ b/drivers/cpufreq/amd-pstate.h
> @@ -71,7 +71,6 @@ struct amd_aperf_mperf {
>   * 		  AMD P-State driver supports preferred core featue.
>   * @epp_cached: Cached CPPC energy-performance preference value
>   * @policy: Cpufreq policy value
> - * @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value
>   *
>   * The amd_cpudata is key private data for each CPU thread in AMD P-State, and
>   * represents all the attributes and goals that AMD P-State requests at runtime.
> @@ -101,7 +100,6 @@ struct amd_cpudata {
>  	/* EPP feature related attributes*/
>  	u8	epp_cached;
>  	u32	policy;
> -	u64	cppc_cap1_cached;
>  	bool	suspended;
>  	u8	epp_default;
>  };


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