linux-kernel - Re: [PATCH v7 03/17] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl

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Message-ID: <67acfbc83ba44_2d1e294c5@dwillia2-xfh.jf.intel.com.notmuch>
Date: Wed, 12 Feb 2025 11:51:36 -0800
From: Dan Williams <dan.j.williams@...el.com>
To: "Bowman, Terry" <terry.bowman@....com>, Dan Williams
	<dan.j.williams@...el.com>, <linux-cxl@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
	<nifan.cxl@...il.com>, <dave@...olabs.net>, <jonathan.cameron@...wei.com>,
	<dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<vishal.l.verma@...el.com>, <bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>,
	<ira.weiny@...el.com>, <oohall@...il.com>, <Benjamin.Cheatham@....com>,
	<rrichter@....com>, <nathan.fontenot@....com>,
	<Smita.KoralahalliChannabasappa@....com>, <lukas@...ner.de>,
	<ming.li@...omail.com>, <PradeepVineshReddy.Kodamati@....com>
Subject: Re: [PATCH v7 03/17] CXL/PCI: Introduce PCIe helper functions
 pcie_is_cxl() and pcie_is_cxl_port()

Bowman, Terry wrote:
[..]
> >
> > Reviewed-by: Dan Williams <dan.j.williams@...el.com>
> Ok, I will add the comment.
> 
> Would you like for me to add the enable/disable internal error logic to cxl_port_probe()? I can but want to confirm.

If it's quick, go ahead. Otherwise I think it is ok to leave it in
aer_probe() for now if only because this is not the only place in the
CXL stack that needs to be fixed up to honor the fact that DVSEC 3 and 7
are only reliable post link-up.

I.e. the other places I know of are:

- cxl_acpi: fails to probe for cachemem component registers on
  disconnected root ports

- cxl_switch_port_probe(): enumerates all dports even though not all may
  be link up yet

So, in the interest of moving this set forward, that wider fix can be
deferred to a later rework series that address all the dynamic DVSEC 3,7
issues.