linux-kernel - Re: [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also display PCIe SBDF

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Message-ID: <6ca5eea6-2219-45f1-ac9b-2fb83f7c4f3b@amd.com>
Date: Wed, 12 Feb 2025 17:34:45 -0600
From: "Bowman, Terry" <terry.bowman@....com>
To: Alison Schofield <alison.schofield@...el.com>
Cc: linux-cxl@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, nifan.cxl@...il.com, dave@...olabs.net,
 jonathan.cameron@...wei.com, dave.jiang@...el.com, vishal.l.verma@...el.com,
 dan.j.williams@...el.com, bhelgaas@...gle.com, mahesh@...ux.ibm.com,
 ira.weiny@...el.com, oohall@...il.com, Benjamin.Cheatham@....com,
 rrichter@....com, nathan.fontenot@....com,
 Smita.KoralahalliChannabasappa@....com, lukas@...ner.de,
 ming.li@...omail.com, PradeepVineshReddy.Kodamati@....com
Subject: Re: [PATCH v7 14/17] cxl/pci: Update CXL Port RAS logging to also
 display PCIe SBDF



On 2/12/2025 5:30 PM, Alison Schofield wrote:
> On Tue, Feb 11, 2025 at 01:24:41PM -0600, Terry Bowman wrote:
>> CXL RAS errors are currently logged using the associated CXL port's name
>> returned from devname(). They are typically named with 'port1', 'port2',
>> etc. to indicate the hierarchial location in the CXL topology. But, this
>> doesn't clearly indicate the CXL card or slot reporting the error.
>>
>> Update the logging to also log the corresponding PCIe devname. This will
>> give a PCIe SBDF or ACPI object name (in case of CXL HB). This will provide
>> details helping users understand which physical slot and card has the
>> error.
>>
>> Below is example output after making these changes.
>>
>> Correctable error example output:
>> cxl_port_aer_correctable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status='Received Error From Physical Layer'
>>
>> Uncorrectable error example output:
>> cxl_port_aer_uncorrectable_error: device=port1 (0000:0c:00.0) parent=root0 (pci0000:0c) status: 'Memory Byte Enable Parity Error' first_error: 'Memory Byte Enable Parity Error'
> snip
>>  
>>  TRACE_EVENT(cxl_port_aer_uncorrectable_error,
>> -	TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),
>> -	TP_ARGS(dev, status, fe, hl),
>> +	TP_PROTO(struct device *cxl_dev, struct device *pcie_dev, u32 status, u32 fe, u32 *hl),
>> +	TP_ARGS(cxl_dev, pcie_dev, status, fe, hl),
>>  	TP_STRUCT__entry(
>> -		__string(devname, dev_name(dev))
>> -		__string(parent, dev_name(dev->parent))
>> +		__string(cxl_name, dev_name(cxl_dev))
>> +		__string(cxl_parent_name, dev_name(cxl_dev->parent))
>> +		__string(pcie_name, dev_name(pcie_dev))
>> +		__string(pcie_parent_name, dev_name(pcie_dev->parent))
> I get the rename of devname->cxl_name and parent->cxl_parent_name
> since now we have pcie names too.  How about making those changes
> in the previous patch where devname and parent are introduced. Then
> this patch doesn't have any changes other than adding the pcie names.
>
> Having said that, should/can this merge with the patch before it?
>
>
> snip
Yes. I'll merge the 2 patches.

Terry