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Message-ID: <6842eded-725f-41be-9249-7fe633093585@kernel.org>
Date: Wed, 12 Feb 2025 07:00:21 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Matthew Gerlach <matthew.gerlach@...ux.intel.com>, lpieralisi@...nel.org,
kw@...ux.com, manivannan.sadhasivam@...aro.org, robh@...nel.org,
bhelgaas@...gle.com, krzk+dt@...nel.org, conor+dt@...nel.org,
dinguyen@...nel.org, joyce.ooi@...el.com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: matthew.gerlach@...era.com, peter.colberg@...era.com
Subject: Re: [PATCH v6 6/7] arm64: dts: agilex: add dts enabling PCIe Root
Port
On 11/02/2025 16:17, Matthew Gerlach wrote:
> Add a device tree enabling PCIe Root Port support on an Agilex F-series
> Development Kit which has the P-tile variant of the PCIe IP.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
> ---
> v6:
> - Fix SPDX header.
...
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> new file mode 100644
> index 000000000000..3588c845cf9c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex7f_socdk_pcie_root_port.dts
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2024, Intel Corporation
> + */
> +
> +#include "socfpga_agilex.dtsi"
> +#include "socfpga_agilex_socdk.dtsi"
> +#include "socfpga_agilex_pcie_root_port.dtsi"
> +
Missing compatible, missing model, missing bindings.
Best regards,
Krzysztof
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