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Message-ID:
<BM1PR01MB2433B351262A2963B192F0A8FEFC2@BM1PR01MB2433.INDPRD01.PROD.OUTLOOK.COM>
Date: Wed, 12 Feb 2025 08:48:39 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Lee Jones <lee@...nel.org>
Cc: kw@...ux.com, u.kleine-koenig@...libre.com, aou@...s.berkeley.edu,
arnd@...db.de, bhelgaas@...gle.com, conor+dt@...nel.org, guoren@...nel.org,
inochiama@...look.com, krzk+dt@...nel.org, lpieralisi@...nel.org,
manivannan.sadhasivam@...aro.org, palmer@...belt.com,
paul.walmsley@...ive.com, pbrobinson@...il.com, robh@...nel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pci@...r.kernel.org, linux-riscv@...ts.infradead.org,
chao.wei@...hgo.com, xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com,
helgaas@...nel.org, Chen Wang <unicornxw@...il.com>
Subject: Re: (subset) [PATCH v3 3/5] dt-bindings: mfd: syscon: Add sg2042 pcie
ctrl compatible
Hello, Lee
I would request that this patch not be merged yet, because it is related
to PCIe changes, and the PCIe changes (bindings and dts) have not been
confirmed yet.
Although this patch is small and will not affect other builds, it is
best to submit it together with the PCIe patch after it is confirmed.
Sorry for the trouble.
Best regards
Chen
On 2025/2/11 22:33, Lee Jones wrote:
> On Wed, 15 Jan 2025 15:07:14 +0800, Chen Wang wrote:
>> Document SOPHGO SG2042 compatible for PCIe control registers.
>> These registers are shared by PCIe controller nodes.
>>
>>
> Applied, thanks!
>
> [3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
> commit: 28df3b1a6aeced4c77a70adc12b4d7b0b69e2ea6
>
> --
> Lee Jones [李琼斯]
>
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