Message-ID:
 <20250212-kernel-upstreaming-add_gpio_support-v1-3-080e724a21f3@blaize.com>
Date: Wed, 12 Feb 2025 13:46:53 +0000
From: Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        James Cowgill <james.cowgill@...ize.com>,
        Matt Redfearn <matthew.redfearn@...ize.com>,
        Neil Jones
	<neil.jones@...ize.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz
 Golaszewski <brgl@...ev.pl>,
        Matt Redfearn <matthew.redfearn@...ize.com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>,
        Nikolaos Pasaloukos
	<nikolaos.pasaloukos@...ize.com>
Subject: [PATCH 3/5] gpio: vsiapb: Add VeriSilicon APB support

VeriSilicon APB v0.2 is a custom GPIO design provided from VeriSilicon
Microelectronics. It has 32 input/output ports which can be
configured as edge or level triggered interrupts. It also provides
a de-bounce feature.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>
---
 MAINTAINERS                |  10 ++
 drivers/gpio/Kconfig       |   9 ++
 drivers/gpio/Makefile      |   1 +
 drivers/gpio/gpio-vsiapb.c | 284 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 304 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index eb75c95f6c455516f7b1c8b3a39ddded5b38e0a9..ad75f7df37d8d63e14846e659666230b137a7ea1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -25343,6 +25343,16 @@ S:	Maintained
 F:	Documentation/networking/vrf.rst
 F:	drivers/net/vrf.c
 
+VSI APB GPIO DRIVER
+M:	James Cowgill <james.cowgill@...ize.com>
+M:	Matt Redfearn <matt.redfearn@...ize.com>
+M:	Neil Jones <neil.jones@...ize.com>
+M:	Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>
+L:	linux-gpio@...r.kernel.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/gpio/vsi,apb-gpio.yaml
+F:	drivers/gpio/gpio-vsiapb.c
+
 VSPRINTF
 M:	Petr Mladek <pmladek@...e.com>
 M:	Steven Rostedt <rostedt@...dmis.org>
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index add5ad29a673c09082a913cb2404073b2034af48..654603f790c7db2481265c2ab7d90eec4be79856 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -769,6 +769,15 @@ config GPIO_VISCONTI
 	help
 	  Say yes here to support GPIO on Tohisba Visconti.
 
+config GPIO_VSIAPB
+	tristate "Verisilicon APB GPIO support"
+	depends on OF_GPIO
+	select GPIO_GENERIC
+	select GPIOLIB_IRQCHIP
+	select IRQ_DOMAIN_HIERARCHY
+	help
+	  Say Y or M here to add support for the Verisilicon APB GPIO device.
+
 config GPIO_WCD934X
 	tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
 	depends on MFD_WCD934X && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index af3ba4d81b583842893ea69e677fbe2abf31bc7b..f0f2dd711c84b9159418154419664c7c1f28340f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -189,6 +189,7 @@ obj-$(CONFIG_GPIO_VIPERBOARD)		+= gpio-viperboard.o
 obj-$(CONFIG_GPIO_VIRTUSER)		+= gpio-virtuser.o
 obj-$(CONFIG_GPIO_VIRTIO)		+= gpio-virtio.o
 obj-$(CONFIG_GPIO_VISCONTI)		+= gpio-visconti.o
+obj-$(CONFIG_GPIO_VSIAPB)		+= gpio-vsiapb.o
 obj-$(CONFIG_GPIO_VX855)		+= gpio-vx855.o
 obj-$(CONFIG_GPIO_WCD934X)		+= gpio-wcd934x.o
 obj-$(CONFIG_GPIO_WHISKEY_COVE)		+= gpio-wcove.o
diff --git a/drivers/gpio/gpio-vsiapb.c b/drivers/gpio/gpio-vsiapb.c
new file mode 100644
index 0000000000000000000000000000000000000000..dab7c579235058724a9b3f07ce302eed5e4f5fce
--- /dev/null
+++ b/drivers/gpio/gpio-vsiapb.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019 VeriSilicon Limited.
+ * Copyright (C) 2025 Blaize, Inc.
+ */
+
+#include <linux/errno.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define GPIO_DIR_REG	0x00
+#define GPIO_CTRL_REG	0x04
+#define GPIO_SET_REG	0x08
+#define GPIO_CLR_REG	0x0C
+#define GPIO_ODATA_REG	0x10
+#define GPIO_IDATA_REG	0x14
+#define GPIO_IEN_REG	0x18
+#define GPIO_IS_REG	0x1C
+#define GPIO_IBE_REG	0x20
+#define GPIO_IEV_REG	0x24
+#define GPIO_RIS_REG	0x28
+#define GPIO_IM_REG	0x2C
+#define GPIO_MIS_REG	0x30
+#define GPIO_IC_REG	0x34
+#define GPIO_DB_REG	0x38
+#define GPIO_DFG_REG	0x3C
+
+#define DRIVER_NAME "vsiapb-gpio"
+
+struct vsiapb_gpio {
+	void __iomem *base;
+	struct gpio_chip gc;
+	int irq;
+};
+
+static inline struct vsiapb_gpio *get_vsiapb_from_irq_data(struct irq_data *d)
+{
+	return gpiochip_get_data(irq_data_get_irq_chip_data(d));
+}
+
+static inline struct vsiapb_gpio *get_vsiapb_from_irq_desc(struct irq_desc *d)
+{
+	return gpiochip_get_data(irq_desc_get_handler_data(d));
+}
+
+static inline u32 vsiapb_gpio_read(struct vsiapb_gpio *chip, unsigned int offset)
+{
+	return readl_relaxed(chip->base + offset);
+}
+
+static inline void vsiapb_gpio_write(struct vsiapb_gpio *chip, unsigned int offset, u32 val)
+{
+	writel_relaxed(val, chip->base + offset);
+}
+
+static inline void vsiapb_gpio_rmw(void __iomem *reg, u32 mask, bool set)
+{
+	u32 val = readl_relaxed(reg);
+
+	if (set)
+		val |= mask;
+	else
+		val &= ~mask;
+
+	writel_relaxed(val, reg);
+}
+
+static void vsiapb_gpio_irq_mask(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1);
+}
+
+static void vsiapb_gpio_irq_unmask(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0);
+}
+
+static void vsiapb_gpio_irq_ack(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	vsiapb_gpio_write(chip, GPIO_IC_REG, BIT(d->hwirq));
+}
+
+static void vsiapb_gpio_irq_enable(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d));
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0);
+	vsiapb_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1);
+}
+
+static void vsiapb_gpio_irq_disable(struct irq_data *d)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0);
+	gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d));
+}
+
+static int vsiapb_gpio_irq_set_type(struct irq_data *d, u32 type)
+{
+	struct vsiapb_gpio *chip = get_vsiapb_from_irq_data(d);
+	u32 edge_level, single_both, fall_rise;
+	int mask = BIT(d->hwirq);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	edge_level = vsiapb_gpio_read(chip, GPIO_IS_REG);
+	single_both = vsiapb_gpio_read(chip, GPIO_IBE_REG);
+	fall_rise = vsiapb_gpio_read(chip, GPIO_IEV_REG);
+
+	switch (type) {
+	case IRQ_TYPE_EDGE_BOTH:
+		edge_level &= ~mask;
+		single_both |= mask;
+		break;
+	case IRQ_TYPE_EDGE_RISING:
+		edge_level &= ~mask;
+		single_both &= ~mask;
+		fall_rise |= mask;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		edge_level &= ~mask;
+		single_both &= ~mask;
+		fall_rise &= ~mask;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		edge_level |= mask;
+		fall_rise |= mask;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		edge_level |= mask;
+		fall_rise &= ~mask;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	vsiapb_gpio_write(chip, GPIO_IS_REG, edge_level);
+	vsiapb_gpio_write(chip, GPIO_IBE_REG, single_both);
+	vsiapb_gpio_write(chip, GPIO_IEV_REG, fall_rise);
+
+	if (type & IRQ_TYPE_LEVEL_MASK)
+		irq_set_handler_locked(d, handle_level_irq);
+	else
+		irq_set_handler_locked(d, handle_edge_irq);
+
+	return 0;
+}
+
+static const struct irq_chip vsiapb_gpio_irqchip = {
+	.name = DRIVER_NAME,
+	.irq_ack = vsiapb_gpio_irq_ack,
+	.irq_mask = vsiapb_gpio_irq_mask,
+	.irq_unmask = vsiapb_gpio_irq_unmask,
+	.irq_set_type = vsiapb_gpio_irq_set_type,
+	.irq_enable = vsiapb_gpio_irq_enable,
+	.irq_disable = vsiapb_gpio_irq_disable,
+	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
+	GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static void vsiapb_gpio_irqhandler(struct irq_desc *desc)
+{
+	struct vsiapb_gpio *gpio = get_vsiapb_from_irq_desc(desc);
+	struct irq_chip *irqchip = irq_desc_get_chip(desc);
+	unsigned long irq_status;
+	int hwirq = 0;
+
+	chained_irq_enter(irqchip, desc);
+	irq_status = vsiapb_gpio_read(gpio, GPIO_RIS_REG);
+	for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio)
+		generic_handle_domain_irq(gpio->gc.irq.domain, hwirq);
+
+	chained_irq_exit(irqchip, desc);
+}
+
+static int vsiapb_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset,
+				    unsigned int debounce)
+{
+	struct vsiapb_gpio *chip = gpiochip_get_data(gc);
+
+	guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
+	vsiapb_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce);
+
+	return 0;
+}
+
+static int vsiapb_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config)
+{
+	u32 debounce;
+
+	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
+		return -ENOTSUPP;
+
+	debounce = pinconf_to_config_argument(config);
+	return vsiapb_gpio_set_debounce(gc, offset, debounce);
+}
+
+static int vsiapb_gpio_probe(struct platform_device *pdev)
+{
+	struct device_node *node = pdev->dev.of_node;
+	struct vsiapb_gpio *chip;
+	struct gpio_chip *gc;
+	int ret;
+
+	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(chip->base))
+		return PTR_ERR(chip->base);
+
+	ret = bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG,
+			 chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG,
+			 chip->base + GPIO_DIR_REG, NULL, 0);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n");
+
+	/* configure the gpio chip */
+	gc = &chip->gc;
+	gc->owner = THIS_MODULE;
+	gc->set_config = vsiapb_gpio_set_config;
+
+	if (of_property_read_bool(node, "interrupt-controller")) {
+		struct gpio_irq_chip *girq;
+
+		chip->irq = platform_get_irq(pdev, 0);
+		if (chip->irq < 0)
+			return chip->irq;
+
+		girq = &gc->irq;
+		gpio_irq_chip_set_chip(girq, &vsiapb_gpio_irqchip);
+		girq->parent_handler = vsiapb_gpio_irqhandler;
+		girq->num_parents = 1;
+		girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
+		if (!girq->parents)
+			return -ENOMEM;
+
+		girq->parents[0] = chip->irq;
+		girq->default_type = IRQ_TYPE_NONE;
+	}
+
+	return devm_gpiochip_add_data(&pdev->dev, gc, chip);
+}
+
+static const struct of_device_id vsiapb_of_match[] = {
+	{ .compatible = "vsi,apb-gpio-0.2", },
+	{ /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, vsiapb_of_match);
+
+static struct platform_driver vsiapb_gpio_driver = {
+	.driver		= {
+		.name	= DRIVER_NAME,
+		.of_match_table = of_match_ptr(vsiapb_of_match),
+	},
+	.probe		= vsiapb_gpio_probe,
+};
+
+module_platform_driver(vsiapb_gpio_driver);
+
+MODULE_AUTHOR("Nikolaos Pasaloukos <nikolaos.pasaloukos@...ize.com>");
+MODULE_DESCRIPTION("Verisilicon APB GPIO driver");
+MODULE_LICENSE("GPL");

-- 
2.43.0

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