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Message-Id: <173947027636.282331.3484983514931257187.b4-ty@kernel.org>
Date: Thu, 13 Feb 2025 23:41:16 +0530
From: Vinod Koul <vkoul@...nel.org>
To: aford173@...il.com, kishon@...nel.org, linux-phy@...ts.infradead.org,
linux-kernel@...r.kernel.org, xiaopeitux@...mail.com
Cc: Pei Xiao <xiaopei01@...inos.cn>
Subject: Re: [PATCH V6] phy: freescale: fsl-samsung-hdmi: Limit PLL lock
detection clock divider to valid range
On Tue, 11 Feb 2025 10:29:48 +0800, xiaopeitux@...mail.com wrote:
> FIELD_PREP() checks that a value fits into the available bitfield,
> but the index div equals to 4,is out of range.
>
> which gcc complains about:
> In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’,
> inlined from ‘fsl_samsung_hdmi_phy_configure’ at
> drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2:
> ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’
> declared with attribute error: FIELD_PREP: value too large for the field
> 542 | _compiletime_assert(condition, msg, __compiletime_assert_,
> __COUNTER__)
> | ^
> ././include/linux/compiler_types.h:523:4: note: in definition of
> macro ‘__compiletime_assert’ 523 | prefix ## suffix();
> | ^~~~~~
> ././include/linux/compiler_types.h:542:2: note: in expansion of macro
> ‘_compiletime_assert’
> 542 | _compiletime_assert(condition, msg, __compiletime_assert_,
> __COUNTER__)
>
> [...]
Applied, thanks!
[1/1] phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to valid range
commit: cd57e4327707126dca3f9517b84274c001d4c184
Best regards,
--
~Vinod
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