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Message-ID: <feefbcf2-e441-4cd1-a3de-40bfd4d7197a@linaro.org>
Date: Thu, 13 Feb 2025 07:10:54 +0000
From: Tudor Ambarus <tudor.ambarus@...aro.org>
To: Denzeel Oliva <wachiturroxd150@...il.com>, andi.shyti@...nel.org,
broonie@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, alim.akhtar@...sung.com, peter.griffin@...aro.org,
andre.draszik@...aro.org, linux-spi@...r.kernel.org,
linux-samsung-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 2/2] spi: s3c64xx: add support exynos990-spi to new
port config data
On 2/12/25 7:12 PM, Denzeel Oliva wrote:
> +static const struct s3c64xx_spi_port_config exynos990_spi_port_config = {
> + /* fifo-depth must be specified in the device tree. */
> + .fifo_depth = 0,
have you tried testing without specifying the fifo_depth in DT?
You'll probably hit a divide by zero at:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/spi/spi-s3c64xx.c#n664
I assume the controller can work with 0 sized FIFO depth, and if so, the
driver has to be updated to allow 0 sized FIFOs.
btw, how did you test the set?
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