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Message-ID: <2885fac1-edb3-4251-8e4a-3da92d3b3974@tuxon.dev>
Date: Thu, 13 Feb 2025 10:28:19 +0200
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, lee@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, sre@...nel.org,
nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com,
p.zabel@...gutronix.de
Cc: linux@...linux.org.uk, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-rtc@...r.kernel.org
Subject: Re: [PATCH v2 14/15] ARM: dts: microchip: sama7d65: Add Reset and
Shutdown and PM support
Hi, Ryan,
On 10.02.2025 23:13, Ryan.Wanner@...rochip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@...rochip.com>
>
> Add support for reset controller, wake up alarm timers, and shutdown
> controller.
>
> Add SRAM, SFR, secumod, UDDRC, and DDR3phy to enable support for low power modes.
Can you split it in individual patches? E.g.
1/ add reset controller
2/ add shutdown controller
3/ add rtc support
4/ add rtt support
5/ add PM support
>
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>
> ---
> arch/arm/boot/dts/microchip/sama7d65.dtsi | 77 +++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
>
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 854b30d15dcd4..1d40235bdab0a 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -46,12 +46,42 @@ slow_xtal: clock-slowxtal {
> };
> };
>
> + ns_sram: sram@...000 {
> + compatible = "mmio-sram";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x100000 0x20000>;
> + ranges;
Please follow order proposed here:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n112
That would be (for this node):
- compatible
- reg
- ranges
- everything else
> + };
> +
> soc {
> compatible = "simple-bus";
> ranges;
> #address-cells = <1>;
> #size-cells = <1>;
>
> + securam: sram@...00800 {
> + compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram";
> + reg = <0xe0000800 0x4000>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0xe0000800 0x4000>;
> + no-memory-wc;
Same here with regards to order and dts coding style.
> + };
> +
> + secumod: secumod@...04000 {
> + compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon";
> + reg = <0xe0004000 0x4000>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + sfrbu: sfr@...08000 {
> + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
> + reg = <0xe0008000 0x20>;
> + };
> +
> pioa: pinctrl@...14000 {
> compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl";
> reg = <0xe0014000 0x800>;
> @@ -76,6 +106,31 @@ pmc: clock-controller@...18000 {
> clock-names = "td_slck", "md_slck", "main_xtal";
> };
>
> + reset_controller: reset-controller@...1d100 {
> + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc";
> + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>;
> + #reset-cells = <1>;
> + clocks = <&clk32k 0>;
> + };
> +
> + shdwc: poweroff@...1d200 {
> + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon";
> + reg = <0xe001d200 0x20>;
> + clocks = <&clk32k 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + atmel,wakeup-rtc-timer;
> + atmel,wakeup-rtt-timer;
> + status = "disabled";
> + };
> +
> + rtt: rtc@...1d300 {
> + compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt";
> + reg = <0xe001d300 0x30>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk32k 0>;
> + };
> +
> clk32k: clock-controller@...1d500 {
> compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc";
> reg = <0xe001d500 0x4>;
> @@ -83,6 +138,18 @@ clk32k: clock-controller@...1d500 {
> #clock-cells = <1>;
> };
>
> + gpbr: gpbr@...1d700 {
> + compatible = "microchip,sama7d65-gpbr", "syscon";
> + reg = <0xe001d700 0x48>;
> + };
> +
> + rtc: rtc@...1d800 {
> + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc";
> + reg = <0xe001d800 0x30>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk32k 1>;
> + };
> +
> sdmmc1: mmc@...08000 {
> compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci";
> reg = <0xe1208000 0x400>;
> @@ -132,6 +199,16 @@ uart6: serial@200 {
> };
> };
>
> + uddrc: uddrc@...00000 {
> + compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc";
> + reg = <0xe3800000 0x4000>;
> + };
> +
> + ddr3phy: ddr3phy@...04000 {
> + compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy";
> + reg = <0xe3804000 0x1000>;
> + };
> +
> gic: interrupt-controller@...11000 {
> compatible = "arm,cortex-a7-gic";
> reg = <0xe8c11000 0x1000>,
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