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Message-ID: <20250214151531.000007d1@huawei.com>
Date: Fri, 14 Feb 2025 15:15:31 +0000
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Terry Bowman <terry.bowman@....com>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pci@...r.kernel.org>, <nifan.cxl@...il.com>, <dave@...olabs.net>,
<dave.jiang@...el.com>, <alison.schofield@...el.com>,
<vishal.l.verma@...el.com>, <dan.j.williams@...el.com>,
<bhelgaas@...gle.com>, <mahesh@...ux.ibm.com>, <ira.weiny@...el.com>,
<oohall@...il.com>, <Benjamin.Cheatham@....com>, <rrichter@....com>,
<nathan.fontenot@....com>, <Smita.KoralahalliChannabasappa@....com>,
<lukas@...ner.de>, <ming.li@...omail.com>,
<PradeepVineshReddy.Kodamati@....com>
Subject: Re: [PATCH v7 08/17] cxl/pci: Map CXL PCIe Upstream Switch Port RAS
registers
On Tue, 11 Feb 2025 13:24:35 -0600
Terry Bowman <terry.bowman@....com> wrote:
> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers.
>
> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a
> pointer to the CXL Upstream Port's mapped RAS registers.
>
> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS
> register mapping. This is similar to the existing
> cxl_dport_init_ras_reporting() but for USP devices.
>
> The USP may have multiple downstream endpoints. Before mapping RAS
> registers check if the registers are already mapped.
>
> Introduce a mutex for synchronizing accesses to the cached RAS
> mapping.
>
> Signed-off-by: Terry Bowman <terry.bowman@....com>
> Reviewed-by: Gregory Price <gourry@...rry.net>
> /**
> * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport
> * @dport: the cxl_dport that needs to be initialized
> @@ -801,7 +819,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport)
> BIT(CXL_CM_CAP_CAP_ID_RAS)))
> dev_err(dport_dev, "Failed to map RAS capability\n");
> mutex_unlock(&ras_init_mutex);
> -
Grumpy hat (it is Friday afternoon). Shouldn't be in this patch!
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL");
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