linux-kernel - Re: [PATCH v6 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties

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Message-ID: <be824a70-380e-84d0-8ada-f849b9453ac0@quicinc.com>
Date: Fri, 14 Feb 2025 14:18:48 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        "Krishna
 Chaitanya Chundru" <krishna.chundru@....qualcomm.com>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Helgaas
	<bhelgaas@...gle.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Lorenzo Pieralisi
	<lpieralisi@...nel.org>,
        Krzysztof Wilczyński
	<kw@...ux.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
        <quic_mrana@...cinc.com>, <quic_vbadigan@...cinc.com>
Subject: Re: [PATCH v6 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane
 equalization preset properties



On 2/14/2025 2:14 PM, Manivannan Sadhasivam wrote:
> On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote:
>> Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data
>> rates used in lane equalization procedure.
>>
>> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
>> ---
>> This patch depends on the this dt binding pull request which got recently
>> merged: https://github.com/devicetree-org/dt-schema/pull/146
>> ---
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 4936fa5b98ff..1b815d4eed5c 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>   			phys = <&pcie3_phy>;
>>   			phy-names = "pciephy";
>>   
>> +			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>,
>> +					  /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
> 
> Why 2 16bit arrays?
> 
Just to keep line length below 100, if I use single line it is crossing
100 lines.

- Krishna Chaitanya.
> - Mani
>