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Message-ID: <1b8b234f-6435-45cf-83e7-8e86c84f075f@linaro.org> Date: Fri, 14 Feb 2025 10:02:44 +0000 From: James Clark <james.clark@...aro.org> To: Yangyu Chen <cyy@...self.name>, Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com> Cc: linux-perf-users@...r.kernel.org, John Garry <john.g.garry@...cle.com>, Will Deacon <will@...nel.org>, Mike Leach <mike.leach@...aro.org>, Leo Yan <leo.yan@...ux.dev>, Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>, Mark Rutland <mark.rutland@....com>, Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>, Adrian Hunter <adrian.hunter@...el.com>, Liang Kan <kan.liang@...ux.intel.com>, Yoshihiro Furudera <fj5100bi@...itsu.com>, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 0/2] perf vendor events arm64: Add A720/A520 events/metrics On 14/02/2025 5:49 am, Yangyu Chen wrote: > > >> On 14 Feb 2025, at 09:12, Namhyung Kim <namhyung@...nel.org> wrote: >> >> Hello, >> >> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >> >> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > The name of PMUs comes from Arm's documentation. I have included these > links in each patch. > >> I remember there's a logic to check the length of hex digits at the end. >> > > Could you provide more details about this? > >> Ian, are you ok with this? >> I think they wouldn't be merged because they're core PMUs, so should be fine? Even though they would otherwise be merged because they're more than 3 hex digits. >> Thanks, >> Namhyung >> >>> >>> Yangyu Chen (2): >>> perf vendor events arm64: Add Cortex-A720 events/metrics >>> perf vendor events arm64: Add Cortex-A520 events/metrics >>> >>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ >>> .../arch/arm64/arm/cortex-a520/exception.json | 18 + >>> .../arm64/arm/cortex-a520/fp_operation.json | 14 + >>> .../arch/arm64/arm/cortex-a520/general.json | 6 + >>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ >>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + >>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ >>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ >>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ >>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ >>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a520/sve.json | 22 + >>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ >>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ >>> .../arch/arm64/arm/cortex-a720/bus.json | 18 + >>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ >>> .../arm64/arm/cortex-a720/fp_operation.json | 22 + >>> .../arch/arm64/arm/cortex-a720/general.json | 10 + >>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ >>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + >>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ >>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ >>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ >>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ >>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ >>> .../arch/arm64/common-and-microarch.json | 15 + >>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >>> 39 files changed, 2263 insertions(+) >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json >>> >>> -- >>> 2.47.2 >>> >
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