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Message-ID: <4b521b49-7104-4f25-82cb-4f9be7b235f4@quicinc.com>
Date: Fri, 14 Feb 2025 09:34:34 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: James Clark <james.clark@...aro.org>
CC: Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Jinlong Mao
	<quic_jinlmao@...cinc.com>, <coresight@...ts.linaro.org>,
        <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        Suzuki K Poulose
	<suzuki.poulose@....com>,
        Mike Leach <mike.leach@...aro.org>,
        "Alexander
 Shishkin" <alexander.shishkin@...ux.intel.com>,
        Maxime Coquelin
	<mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>
Subject: Re: [PATCH v10 4/7] Coresight: Introduce a new struct coresight_path



On 2/14/2025 12:00 AM, James Clark wrote:
> 
> 
> On 07/02/2025 6:42 am, Jie Gan wrote:
>> Add 'struct coresight_path' to store the data that is needed by
>> coresight_enable_path/coresight_disable_path. The structure will be
>> transmitted to any required devices to enable related funcationalities.
>>
>> The trace_id will be allocated after the path is built. Consequently,
>> The ETM3x and ETM4x devices will directly read the trace_id from path
>> which result in etm_read_alloc_trace_id and etm4_read_alloc_trace_id
>> being deleted.
>>
>> Co-developed-by: James Clark <james.clark@...aro.org>
>> Signed-off-by: James Clark <james.clark@...aro.org>
>> Signed-off-by: Jie Gan <quic_jiegan@...cinc.com>
>> ---
>>   drivers/hwtracing/coresight/coresight-core.c  | 106 +++++++++++++-----
>>   drivers/hwtracing/coresight/coresight-dummy.c |   5 +-
>>   .../hwtracing/coresight/coresight-etm-perf.c  |  30 +++--
>>   .../hwtracing/coresight/coresight-etm-perf.h  |   2 +-
>>   drivers/hwtracing/coresight/coresight-etm.h   |   1 -
>>   .../coresight/coresight-etm3x-core.c          |  54 ++-------
>>   .../coresight/coresight-etm4x-core.c          |  54 ++-------
>>   drivers/hwtracing/coresight/coresight-etm4x.h |   1 -
>>   drivers/hwtracing/coresight/coresight-priv.h  |  12 +-
>>   drivers/hwtracing/coresight/coresight-stm.c   |   3 +-
>>   drivers/hwtracing/coresight/coresight-sysfs.c |  17 ++-
>>   drivers/hwtracing/coresight/coresight-tpdm.c  |   3 +-
>>   include/linux/coresight.h                     |  12 +-
>>   13 files changed, 143 insertions(+), 157 deletions(-)
>>
> [...]
>> @@ -352,7 +352,7 @@ static void *etm_setup_aux(struct perf_event 
>> *event, void **pages,
>>        * CPUs, we can handle it and fail the session.
>>        */
>>       for_each_cpu(cpu, mask) {
>> -        struct list_head *path;
>> +        struct coresight_path *path;
>>           struct coresight_device *csdev;
>>           csdev = per_cpu(csdev_src, cpu);
>> @@ -405,15 +405,15 @@ static void *etm_setup_aux(struct perf_event 
>> *event, void **pages,
>>               cpumask_clear_cpu(cpu, mask);
>>               continue;
>>           }
>> -
>>           /* ensure we can allocate a trace ID for this CPU */
>> -        trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink- 
>> >perf_sink_id_map);
>> -        if (!IS_VALID_CS_TRACE_ID(trace_id)) {
>> +        trace_id = coresight_path_assign_trace_id(path, CS_MODE_PERF);
>> +
>> +        /* Can be 0 and valid, ETE doesn't need an ID */
>> +        if (trace_id < 0) {
> 
> Not sure why I wrote it like this, but I think we should leave it as it 
> was with !IS_VALID_CS_TRACE_ID(). Even with ETE it calls the trace ID 
> allocator, so nothing has changed here.
> 
Sure, Will restore. For ETE or ETM, we dont need traverse the path, just 
directly allocate the trace id based on cpu id.

Jie



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