linux-kernel - [PATCH] riscv: dts: starfive: fml13v01: increase eMMC bus speed

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Message-Id: <20250215-fml13v01_emmc_speed-v1-1-e3bd224ae0e8@hotmail.com>
Date: Sat, 15 Feb 2025 10:46:47 +0100
From: Maud Spierings via B4 Relay <devnull+maud_spierings.hotmail.com@...nel.org>
To: Conor Dooley <conor@...nel.org>, Emil Renner Berthing <kernel@...il.dk>, 
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Paul Walmsley <paul.walmsley@...ive.com>, 
 Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
 Alexandre Ghiti <alex@...ti.fr>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, Maud Spierings <maud_spierings@...mail.com>
Subject: [PATCH] riscv: dts: starfive: fml13v01: increase eMMC bus speed

From: Maud Spierings <maud_spierings@...mail.com>

The assigned clock speed of 50 MHz is and max-frequency of 100MHz are
limitting this interface which is SDIO 5.0 capable. Sadly at 200MHz it
fails to mount an eMMC drive, 150MHz (really 132 MHz) is the highest it
was able to get.

This improves the seq read/write performance by 2x~

Signed-off-by: Maud Spierings <maud_spierings@...mail.com>
---
I put this in this specific dts instead of the common one as I cannot
test if other boards are also able to handle these speeds.

This patch depends on [1]

[1]: https://lore.kernel.org/all/20250207093618.126636-1-sandie.cao@deepcomputing.io/
---
 arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 8d9ce8b69a71be78ca57618ae842c9f415648450..1f4bac9f89463a6af844b8f1743bdfa659e612ab 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,11 @@ / {
 	compatible = "deepcomputing,fml13v01", "starfive,jh7110";
 };
 
+&mmc0 {
+	max-frequency = <200000000>;
+	assigned-clock-rates = <150000000>;
+};
+
 &pcie1 {
 	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
 	phys = <&pciephy1>;

---
base-commit: 0bc08ec1ff5a32449d2b04704173dbf3ebd6b014
change-id: 20250215-fml13v01_emmc_speed-67812bd9b404

Best regards,
-- 
Maud Spierings <maud_spierings@...mail.com>