linux-kernel - Re: [PATCH v3 3/4] drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK

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Message-ID: <5a5ad8f0-180f-4577-955c-7e26ebac129b@quicinc.com>
Date: Sat, 15 Feb 2025 09:41:48 -0800
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Rob Clark
	<robdclark@...il.com>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        Sean
 Paul <sean@...rly.run>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David
 Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Jonathan Marek
	<jonathan@...ek.ca>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
        <freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
        Rob Clark
	<robdclark@...omium.org>
Subject: Re: [PATCH v3 3/4] drm/msm/dsi/phy: Do not overwite PHY_CMN_CLK_CFG1
 when choosing bitclk source



On 2/14/2025 7:08 AM, Krzysztof Kozlowski wrote:
> PHY_CMN_CLK_CFG1 register has four fields being used in the driver: DSI
> clock divider, source of bitclk and two for enabling the DSI PHY PLL
> clocks.
> 
> dsi_7nm_set_usecase() sets only the source of bitclk, so should leave
> all other bits untouched.  Use newly introduced
> dsi_pll_cmn_clk_cfg1_update() to update respective bits without
> overwriting the rest.
> 
> While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to
> make the code more readable and obvious.
> 
> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> 
> ---
> 
> Changes in v3:
> 1. Define bitfields (move here parts from patch #4)
> ---
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c             | 4 ++--
>   drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 1 +
>   2 files changed, 3 insertions(+), 2 deletions(-)
> 

Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>