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Message-ID: <86ikp9sqco.wl-maz@kernel.org>
Date: Sun, 16 Feb 2025 18:21:11 +0000
From: Marc Zyngier <maz@...nel.org>
To: Dmitry Osipenko <dmitry.osipenko@...labora.com>
Cc: Heiko Stuebner <heiko@...ech.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	devicetree@...r.kernel.org,
	linux-rockchip@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Kever Yang <kever.yang@...k-chips.com>,
	XiaoDong Huang <derrick.huang@...k-chips.com>,
	Peter Geis <pgwipeout@...il.com>,
	Robin Murphy <robin.murphy@....com>,
	kernel@...labora.com
Subject: Re: [PATCH v1 1/4] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround

On Sun, 16 Feb 2025 15:25:53 +0000,
Dmitry Osipenko <dmitry.osipenko@...labora.com> wrote:
> 
> On 2/16/25 12:55, Marc Zyngier wrote:
> > On Sat, 15 Feb 2025 23:54:28 +0000,
> > Dmitry Osipenko <dmitry.osipenko@...labora.com> wrote:
> >>
> >> Rockchip RK3566/RK3568 GIC600 integration has DDR addressing
> >> limited to first 4GB of DRAM. Rockchip assigned Erratum ID #3568002
> >> for this issue. Add driver quirk for this Rockchip GIC Erratum.
> > 
> > Thanks for taking the time to submit this. It only took 5 years for
> > this erratum to be published...
> 
> The erratum document itself actually is dated by 5 years ago. Only wish
> the doc was made publicly available, which would've accelerated the
> upstreaming process.

The funny thing is that RockChip was very public about the issue in
2019, but refused to acknowledge that it was a bug (see the list
archives). 5 years lost with bad performance and bad upstream support,
only to finally admit the bleeding obvious.

On the other hand, we're getting close to 10 years of rk3399, and the
botched integration of GIC500 still hasn't been officially disclosed.
I guess this counts as progress ;-).

	M.

-- 
Without deviation from the norm, progress is not possible.

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