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Message-Id: <20250216-imx214_clk_freq-v1-2-812f40f07db3@apitzsch.eu>
Date: Sun, 16 Feb 2025 19:46:45 +0100
From: André Apitzsch via B4 Relay <devnull+git.apitzsch.eu@...nel.org>
To: Ricardo Ribalda <ribalda@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
linux-media@...r.kernel.org, linux-kernel@...r.kernel.org,
André Apitzsch <git@...tzsch.eu>
Subject: [PATCH 2/4] media: i2c: imx214: Prepare for variable clock
frequency
From: André Apitzsch <git@...tzsch.eu>
Move clock frequency related parameters out of the constant register
sequences, such that the hard coded external clock frequency can be
replaced by a variable in the next commit.
Signed-off-by: André Apitzsch <git@...tzsch.eu>
---
drivers/media/i2c/imx214.c | 64 ++++++++++++++++++++++++++++------------------
1 file changed, 39 insertions(+), 25 deletions(-)
diff --git a/drivers/media/i2c/imx214.c b/drivers/media/i2c/imx214.c
index 14a4c5094799014da38ab1beec401f0d923c2152..53b6b427f263a8ad7e3a0d1f711ece234601100e 100644
--- a/drivers/media/i2c/imx214.c
+++ b/drivers/media/i2c/imx214.c
@@ -320,17 +320,6 @@ static const struct cci_reg_sequence mode_4096x2304[] = {
{ IMX214_REG_DIG_CROP_WIDTH, 4096 },
{ IMX214_REG_DIG_CROP_HEIGHT, 2304 },
- { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV },
- { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV },
- { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV },
- { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY },
- { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV },
- { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV },
- { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
-
- { IMX214_REG_REQ_LINK_BIT_RATE,
- IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) },
-
{ CCI_REG8(0x3A03), 0x09 },
{ CCI_REG8(0x3A04), 0x50 },
{ CCI_REG8(0x3A05), 0x01 },
@@ -384,17 +373,6 @@ static const struct cci_reg_sequence mode_1920x1080[] = {
{ IMX214_REG_DIG_CROP_WIDTH, 1920 },
{ IMX214_REG_DIG_CROP_HEIGHT, 1080 },
- { IMX214_REG_VTPXCK_DIV, IMX214_DEFAULT_VTPXCK_DIV },
- { IMX214_REG_VTSYCK_DIV, IMX214_DEFAULT_VTSYCK_DIV },
- { IMX214_REG_PREPLLCK_VT_DIV, IMX214_DEFAULT_PREPLLCK_VT_DIV },
- { IMX214_REG_PLL_VT_MPY, IMX214_DEFAULT_PLL_VT_MPY },
- { IMX214_REG_OPPXCK_DIV, IMX214_DEFAULT_OPPXCK_DIV },
- { IMX214_REG_OPSYCK_DIV, IMX214_DEFAULT_OPSYCK_DIV },
- { IMX214_REG_PLL_MULT_DRIV, IMX214_PLL_SINGLE },
-
- { IMX214_REG_REQ_LINK_BIT_RATE,
- IMX214_LINK_BIT_RATE_MBPS(IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ)) },
-
{ CCI_REG8(0x3A03), 0x04 },
{ CCI_REG8(0x3A04), 0xF8 },
{ CCI_REG8(0x3A05), 0x02 },
@@ -428,9 +406,6 @@ static const struct cci_reg_sequence mode_table_common[] = {
/* ATR setting */
{ IMX214_REG_ATR_FAST_MOVE, 2 },
- /* external clock setting */
- { IMX214_REG_EXCK_FREQ, IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000) },
-
/* global setting */
/* basic config */
{ IMX214_REG_MASK_CORR_FRAMES, IMX214_CORR_FRAMES_MASK },
@@ -800,6 +775,30 @@ static int imx214_entity_init_state(struct v4l2_subdev *subdev,
return 0;
}
+static int imx214_set_clock(struct imx214 *imx214)
+{
+ int ret = 0;
+
+ cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV,
+ IMX214_DEFAULT_VTPXCK_DIV, &ret);
+ cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV,
+ IMX214_DEFAULT_VTSYCK_DIV, &ret);
+ cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV,
+ IMX214_DEFAULT_PREPLLCK_VT_DIV, &ret);
+ cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY,
+ IMX214_DEFAULT_PLL_VT_MPY, &ret);
+ cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV,
+ IMX214_DEFAULT_OPPXCK_DIV, &ret);
+ cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV,
+ IMX214_DEFAULT_OPSYCK_DIV, &ret);
+ cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV,
+ IMX214_PLL_SINGLE, &ret);
+ cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ,
+ IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000), &ret);
+
+ return ret;
+}
+
static int imx214_update_digital_gain(struct imx214 *imx214, u32 val)
{
int ret = 0;
@@ -1032,6 +1031,7 @@ static int imx214_start_streaming(struct imx214 *imx214)
const struct v4l2_mbus_framefmt *fmt;
struct v4l2_subdev_state *state;
const struct imx214_mode *mode;
+ int link_bit_rate;
int ret;
ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
@@ -1041,6 +1041,20 @@ static int imx214_start_streaming(struct imx214 *imx214)
return ret;
}
+ ret = imx214_set_clock(imx214);
+ if (ret) {
+ dev_err(imx214->dev, "failed to configure clock %d\n", ret);
+ return ret;
+ }
+
+ link_bit_rate = IMX214_LINK_BIT_RATE(IMX214_DEFAULT_CLK_FREQ);
+ ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE,
+ IMX214_LINK_BIT_RATE_MBPS(link_bit_rate), NULL);
+ if (ret) {
+ dev_err(imx214->dev, "failed to configure link bit rate\n");
+ return ret;
+ }
+
ret = cci_write(imx214->regmap, IMX214_REG_CSI_LANE_MODE,
IMX214_CSI_4_LANE_MODE, NULL);
if (ret) {
--
2.48.1
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