linux-kernel - RE: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920

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Message-ID: <02c401db8118$5fcd7460$1f685d20$@samsung.com>
Date: Mon, 17 Feb 2025 14:15:56 +0530
From: "Devang Tailor" <dev.tailor@...sung.com>
To: "'Alim Akhtar'" <alim.akhtar@...sung.com>, "'Krzysztof Kozlowski'"
	<krzk@...nel.org>, "'Sudeep Holla'" <sudeep.holla@....com>
Cc: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
	<devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-samsung-soc@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<faraz.ata@...sung.com>
Subject: RE: [PATCH v2] arm64: dts: add cpu cache information to
 ExynosAuto-v920

Hi Krzysztof,


> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@...sung.com>
> Sent: 05 February 2025 21:41
> To: 'Krzysztof Kozlowski' <krzk@...nel.org>; 'Sudeep Holla'
> <sudeep.holla@....com>
> Cc: 'Devang Tailor' <dev.tailor@...sung.com>; robh@...nel.org;
> krzk+dt@...nel.org; conor+dt@...nel.org; devicetree@...r.kernel.org; linux-
> arm-kernel@...ts.infradead.org; linux-samsung-soc@...r.kernel.org; linux-
> kernel@...r.kernel.org; faraz.ata@...sung.com
> Subject: RE: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-
> v920
> 
> Hi Krzysztof
> 
> > -----Original Message-----
> > From: Krzysztof Kozlowski <krzk@...nel.org>
> > Sent: Wednesday, February 5, 2025 9:22 PM
> > To: Sudeep Holla <sudeep.holla@....com>; Alim Akhtar
> > <alim.akhtar@...sung.com>
> > Cc: 'Devang Tailor' <dev.tailor@...sung.com>; robh@...nel.org;
> > krzk+dt@...nel.org; conor+dt@...nel.org; devicetree@...r.kernel.org;
> > linux-arm-kernel@...ts.infradead.org;
> > linux-samsung-soc@...r.kernel.org;
> > linux-kernel@...r.kernel.org; faraz.ata@...sung.com
> > Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to
> > ExynosAuto-v920
> >
> > On 31/01/2025 14:27, Sudeep Holla wrote:
> > >>>
> > >> [snip]
> > >>  > +		l3_cache_cl0: l3-cache0 {
> > >> You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and
> > >> Remove the specific node for CL1, because both are same.
> > >>
> > >
> > > What do you mean by "both are same" ?
> > > Do you mean both have exact same properties but are physically
> > > different caches ? OR Do you mean it is just one shared cache ?
> > >
> > > If former, we still need distinct node to get the cacheinfo about
> > > shareability correct. If this is about avoiding duplication of
> > > errors, you can probably define some macro and avoid it, but we need
> > > 2 nodes in the devicetree.
> > >
> > > If latter, you suggestion is correct.
> >
> > No answers here, so I drop this patch from my queue.
> >
> It took sometime to get the confirmation internally (because of new year
> holiday) Just replied to Sudeep. It will be great if you can consider this patch
> for this cycle.
> Thanks!
> 
Is there anything else need to be done for this patch or do you suggest me to re-send this patch again?

> > Best regards,
> > Krzysztof