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Message-ID: <20250217105354.551788-12-thierry.bultel.yh@bp.renesas.com>
Date: Mon, 17 Feb 2025 11:52:12 +0100
From: Thierry Bultel <thierry.bultel.yh@...renesas.com>
To: thierry.bultel@...atsea.fr,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
Thierry Bultel <thierry.bultel.yh@...renesas.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v2 11/13] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC
Add the initial dtsi for the RZ/T2H Soc:
- gic
- armv8-timer
- cpg clock
- sci0 uart
also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
all 4 CPUs enabled, for consistency with later support of -m24
and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
and that will use /delete-node/ to disable the missing CPUs.
Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 129 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi | 13 ++
2 files changed, 142 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
new file mode 100644
index 000000000000..0450517f1a69
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r9a09g077-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r9a09g077";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ l3_ca55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-level = <3>;
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&l3_ca55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&l3_ca55>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ device_type = "cpu";
+ next-level-cache = <&l3_ca55>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ device_type = "cpu";
+ next-level-cache = <&l3_ca55>;
+ enable-method = "psci";
+ };
+ };
+
+ loco_clk: loco {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sci0: serial@...05000 {
+ compatible = "renesas,r9a09g077-sci";
+ reg = <0 0x80005000 0 0x400>;
+ interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "tei";
+ clocks = <&cpg CPG_MOD 108>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@...80000 {
+ compatible = "renesas,r9a09g077-cpg-mssr";
+ reg = <0 0x80280000 0 0x1000>,
+ <0 0x81280000 0 0x9000>;
+ clocks = <&extal_clk>, <&loco_clk>;
+ clock-names = "extal", "loco";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ gic: interrupt-controller@...00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x83000000 0 0x40000>,
+ <0x0 0x83040000 0 0x160000>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
new file mode 100644
index 000000000000..6f4a11b39d12
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/T2H 4-core SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a09g077.dtsi"
+
+/ {
+ compatible = "renesas,r9a09g077m44", "renesas,r9a09g077";
+};
--
2.43.0
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