linux-kernel - [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region

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Message-ID: <20250218132356.1809075-11-rrichter@amd.com>
Date: Tue, 18 Feb 2025 14:23:51 +0100
From: Robert Richter <rrichter@....com>
To: Alison Schofield <alison.schofield@...el.com>, Vishal Verma
	<vishal.l.verma@...el.com>, Ira Weiny <ira.weiny@...el.com>, Dan Williams
	<dan.j.williams@...el.com>, Jonathan Cameron <Jonathan.Cameron@...wei.com>,
	Dave Jiang <dave.jiang@...el.com>, Davidlohr Bueso <dave@...olabs.net>
CC: <linux-cxl@...r.kernel.org>, <linux-kernel@...r.kernel.org>, Gregory Price
	<gourry@...rry.net>, "Fabio M. De Francesco"
	<fabio.m.de.francesco@...ux.intel.com>, Terry Bowman <terry.bowman@....com>,
	Robert Richter <rrichter@....com>
Subject: [PATCH v2 10/15] cxl/region: Use root decoders interleaving parameters to create a region

Endpoints requiring address translation might not be aware of the
system's interleaving configuration. Instead, interleaving can be
configured on an upper memory domain (from an endpoint view) and thus
is not visible to the endpoint. For region creation this might cause
an invalid interleaving config that does not match the CFMWS entries.

Use the interleaving configuration of the root decoders to create a
region which bases on CFMWS entries. This always matches the system's
interleaving configuration and is independent of the underlying memory
topology.

Signed-off-by: Robert Richter <rrichter@....com>
---
 drivers/cxl/core/region.c | 39 ++++++++++++++++++++++++++++++++++-----
 drivers/cxl/cxl.h         |  2 ++
 2 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index 6e0434eee6df..3afcc9ca06ae 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -1749,6 +1749,15 @@ static int cxl_region_validate_position(struct cxl_region *cxlr,
 		}
 	}
 
+	if (p->interleave_ways != cxled->interleave_ways ||
+	    p->interleave_granularity != cxled->interleave_granularity ) {
+		dev_dbg(&cxlr->dev, "interleaving config mismatch with %s: ways: %d:%d granularity: %d:%d\n",
+			dev_name(&cxled->cxld.dev), p->interleave_ways,
+			cxled->interleave_ways, p->interleave_granularity,
+			cxled->interleave_granularity);
+		return -ENXIO;
+	}
+
 	return 0;
 }
 
@@ -1852,7 +1861,7 @@ static int match_switch_decoder_by_range(struct device *dev,
 }
 
 static int find_pos_and_ways(struct cxl_port *port, struct range *range,
-			     int *pos, int *ways)
+			     int *pos, int *ways, int *granularity)
 {
 	struct cxl_switch_decoder *cxlsd;
 	struct cxl_port *parent;
@@ -1873,6 +1882,7 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
 	}
 	cxlsd = to_cxl_switch_decoder(dev);
 	*ways = cxlsd->cxld.interleave_ways;
+	*granularity = cxlsd->cxld.interleave_granularity;
 
 	for (int i = 0; i < *ways; i++) {
 		if (cxlsd->target[i] == port->parent_dport) {
@@ -1896,6 +1906,8 @@ static int find_pos_and_ways(struct cxl_port *port, struct range *range,
 struct cxl_interleave_context {
 	struct range *hpa_range;
 	int pos;
+	int interleave_ways;
+	int interleave_granularity;
 };
 
 /**
@@ -1914,13 +1926,17 @@ struct cxl_interleave_context {
  * the topology from the endpoint to the root decoder and iteratively
  * applying the function for each port.
  *
+ * Calculation of interleaving ways:
+ *
+ *    interleave_ways = interleave_ways * parent_ways;
+ *
  * Return: position >= 0 on success
  *	   -ENXIO on failure
  */
 static int cxl_port_calc_interleave(struct cxl_port *port,
 				    struct cxl_interleave_context *ctx)
 {
-	int parent_ways = 0, parent_pos = 0;
+	int parent_ways = 0, parent_pos = 0, parent_granularity = 0;
 	int rc;
 
 	/*
@@ -1955,12 +1971,23 @@ static int cxl_port_calc_interleave(struct cxl_port *port,
 	if (is_cxl_root(port))
 		return 0;
 
-	rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways);
+	rc = find_pos_and_ways(port, ctx->hpa_range, &parent_pos, &parent_ways,
+			&parent_granularity);
 	if (rc)
 		return rc;
 
 	ctx->pos = ctx->pos * parent_ways + parent_pos;
 
+	if (ctx->interleave_ways)
+		ctx->interleave_ways *= parent_ways;
+	else
+		ctx->interleave_ways = parent_ways;
+
+	if (ctx->interleave_granularity)
+		ctx->interleave_granularity *= ctx->interleave_ways;
+	else
+		ctx->interleave_granularity = parent_granularity;
+
 	return ctx->pos;
 }
 
@@ -3407,6 +3434,8 @@ static int cxl_endpoint_decoder_initialize(struct cxl_endpoint_decoder *cxled)
 	cxled->cxlrd = to_cxl_root_decoder(&cxld->dev);
 	cxled->spa_range = hpa;
 	cxled->pos = ctx.pos;
+	cxled->interleave_ways = ctx.interleave_ways;
+	cxled->interleave_granularity = ctx.interleave_granularity;
 
 	return 0;
 }
@@ -3508,8 +3537,8 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
 	}
 
 	p->res = res;
-	p->interleave_ways = cxled->cxld.interleave_ways;
-	p->interleave_granularity = cxled->cxld.interleave_granularity;
+	p->interleave_ways = cxled->interleave_ways;
+	p->interleave_granularity = cxled->interleave_granularity;
 	p->state = CXL_CONFIG_INTERLEAVE_ACTIVE;
 
 	rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 7303aec1c31c..31afd71c3c8e 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -399,6 +399,8 @@ struct cxl_endpoint_decoder {
 	enum cxl_decoder_state state;
 	int part;
 	int pos;
+	int interleave_ways;
+	int interleave_granularity;
 };
 
 /**
-- 
2.39.5